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authorMichael Buesch <m@bues.ch>2019-08-14 21:31:48 +0200
committerMichael Buesch <m@bues.ch>2019-08-14 21:31:48 +0200
commitefa9f177f84ddc2a44d220d8044a8e78959307d3 (patch)
tree8134cb6624e23339db35b4120d6215848234e977
parent5148a8597b025aa726a393d50a6fe56010d3a06b (diff)
downloadpyprofibus-efa9f177f84ddc2a44d220d8044a8e78959307d3.tar.xz
pyprofibus-efa9f177f84ddc2a44d220d8044a8e78959307d3.zip
crcgen: Fix make rule
Signed-off-by: Michael Buesch <m@bues.ch>
-rw-r--r--phy_fpga/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/phy_fpga/Makefile b/phy_fpga/Makefile
index e468279..bbee2f7 100644
--- a/phy_fpga/Makefile
+++ b/phy_fpga/Makefile
@@ -63,7 +63,7 @@ PLL_MOD_V :=
endif
crcgen.stamp:
- $(TEST) -d ./crcgen || $(GIT) submodule update --init
+ $(TEST) -f ./crcgen/crcgen/__main__.py || $(GIT) submodule update --init
$(TOUCH) $@
crc8_func.v: crcgen.stamp
bues.ch cgit interface