aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* phy-fpga: Add CRC error bitphy_fpgaMichael Buesch2 days3-2/+24
* phy-fpga: Calculate and check baud rate errorMichael Buesch3 days1-2/+14
* phy-fpga: Handle more errorsMichael Buesch3 days3-8/+11
* phy-fpga: Improve robustnessMichael Buesch4 days3-20/+19
* fpga driver: Add more error handlingMichael Buesch5 days4-35/+135
* crcgen: Run tests in parallelMichael Buesch5 days1-29/+44
* crcgen: Move all tests to test moduleMichael Buesch5 days2-104/+104
* crcgen: Add testMichael Buesch5 days2-0/+225
* crcgen: Move reference implementation to its own classMichael Buesch5 days1-88/+129
* crcgen: Fix generator for left-shift with size bigger than 8 bitsMichael Buesch5 days1-1/+1
* crcgen: Cleanup generated Python codeMichael Buesch5 days1-12/+17
* crcgen: More cleanupsMichael Buesch5 days1-38/+59
* crcgen: Use unsigned calculation in CMichael Buesch5 days1-3/+7
* crcgen: Require at least one output optionMichael Buesch5 days1-2/+2
* crcgen: Fix verilog constantsMichael Buesch5 days1-1/+1
* make: Use crc algorithm specifierMichael Buesch5 days1-1/+1
* crcgen: Add common algorithm parametersMichael Buesch5 days1-15/+72
* crcgen: Fix optimizer, if all parts of a term have been optimized out.Michael Buesch5 days1-0/+4
* crcgen: Fix typoMichael Buesch5 days1-2/+2
* crcgen: Remove flippingMichael Buesch5 days1-19/+4
* crcgen: CleanupsMichael Buesch5 days1-41/+37
* crcgen: Add exception classMichael Buesch5 days1-3/+6
* crcgen: Add abstract base class for bitsMichael Buesch5 days1-11/+10
* crcgen: Remove equality operator from dataclassesMichael Buesch5 days1-15/+0
* crcgen: Rewrite flattening optimizerMichael Buesch5 days1-27/+27
* crcgen: Minor cleanupMichael Buesch5 days1-15/+15
* crcgen: Clean up optimizerMichael Buesch5 days1-12/+22
* crcgen: Extend CRC generatorMichael Buesch5 days1-33/+120
* crcgen: Extend reference implementationMichael Buesch5 days1-16/+83
* phy-fpga: Add TX-active output pinMichael Buesch5 days1-10/+13
* fpga-driver: Reset RX buffer on invalid telegram lengthMichael Buesch5 days1-0/+3
* fpga-driver: Move code to separate modulesMichael Buesch5 days5-547/+613
* fpga: Invert ifdef logicMichael Buesch5 days1-3/+3
* fpga: Also reset state machine before soft resetMichael Buesch5 days1-0/+1
* fpga-driver: More fixes to I/O logicMichael Buesch5 days2-82/+237
* fpga: Add flags for hard resetMichael Buesch5 days2-22/+52
* fpga: Add bit for status signallingMichael Buesch5 days2-21/+36
* fpga/pb: Change control message buffer handlingMichael Buesch5 days1-83/+80
* fpga: re-arrange pinsMichael Buesch5 days3-35/+43
* fpga: Move target specific code to target moduleMichael Buesch5 days1-31/+114
* fpga/pb: Make debug interface conditional on DEBUG defineMichael Buesch5 days1-0/+6
* fpga: Add DEBUG defineMichael Buesch5 days1-1/+3
* fpga: Add LED blinkerMichael Buesch5 days2-1/+85
* uart: Limit sym timerMichael Buesch5 days1-2/+6
* Switch to xz dist archiveMichael Buesch5 days1-1/+1
* release: Add buildMichael Buesch5 days2-1/+26
* fpga: small makefile cleanupsMichael Buesch5 days1-6/+7
* fpga: Add prefixes to generated filesMichael Buesch5 days1-9/+9
* fpga/crc: Add arg hex parserMichael Buesch5 days2-3/+7
* fpga: Add basic support for other targetsMichael Buesch5 days2-8/+28
bues.ch cgit interface