From efa9f177f84ddc2a44d220d8044a8e78959307d3 Mon Sep 17 00:00:00 2001
From: Michael Buesch <m@bues.ch>
Date: Wed, 14 Aug 2019 21:31:48 +0200
Subject: crcgen: Fix make rule

Signed-off-by: Michael Buesch <m@bues.ch>
---
 phy_fpga/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/phy_fpga/Makefile b/phy_fpga/Makefile
index e468279..bbee2f7 100644
--- a/phy_fpga/Makefile
+++ b/phy_fpga/Makefile
@@ -63,7 +63,7 @@ PLL_MOD_V		:=
 endif
 
 crcgen.stamp:
-	$(TEST) -d ./crcgen || $(GIT) submodule update --init
+	$(TEST) -f ./crcgen/crcgen/__main__.py || $(GIT) submodule update --init
 	$(TOUCH) $@
 
 crc8_func.v: crcgen.stamp
-- 
cgit v1.2.3