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authorMichael Buesch <mb@bu3sch.de>2010-01-31 23:05:55 +0100
committerMichael Buesch <mb@bu3sch.de>2010-01-31 23:05:55 +0100
commit81743dc1458f5ba6161a9c6161884aa9df021a71 (patch)
tree4b6ffa72ed01fb353ec420d36b218e1c1e3919d9
parent85880258cc0ee4abcf4c4bcb00717b6277e0467c (diff)
downloadtoprammer-81743dc1458f5ba6161a9c6161884aa9df021a71.tar.xz
toprammer-81743dc1458f5ba6161a9c6161884aa9df021a71.zip
Document FPGA data writing
Signed-off-by: Michael Buesch <mb@bu3sch.de>
-rw-r--r--chip_atmega8dip28.py6
-rw-r--r--reverse-engineering/HWPROTOCOL2
-rwxr-xr-xtoprammer4
3 files changed, 9 insertions, 3 deletions
diff --git a/chip_atmega8dip28.py b/chip_atmega8dip28.py
index 3c6483c..d99e60b 100644
--- a/chip_atmega8dip28.py
+++ b/chip_atmega8dip28.py
@@ -213,7 +213,7 @@ class ATMega8DIP28(Chip):
self.__setBS1(0)
self.__setXA0(0)
self.__setXA1(0)
- self.top.send("\x10" + chr(addrLow & 0xFF))
+ self.top.cmdFPGAWriteByte(addrLow & 0xFF)
self.__pulseXTAL1()
def __loadAddrHigh(self, addrHigh):
@@ -221,7 +221,7 @@ class ATMega8DIP28(Chip):
self.__setBS1(1)
self.__setXA0(0)
self.__setXA1(0)
- self.top.send("\x10" + chr(addrHigh & 0xFF))
+ self.top.cmdFPGAWriteByte(addrHigh & 0xFF)
self.__pulseXTAL1()
def __loadCommand(self, command):
@@ -230,7 +230,7 @@ class ATMega8DIP28(Chip):
self.top.send("\x34")
self.__setXA0(0)
self.__setXA1(1)
- self.top.send("\x10" + chr(command))
+ self.top.cmdFPGAWriteByte(command)
self.__pulseXTAL1()
def __setB1(self, high):
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index a28f348..938a7b8 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -8,6 +8,8 @@ TOP2049 USB protocol (incomplete)
01 >= Read a byte from the FPGA into the status register.
+10xx >= Write a byte (xx) to the FPGA.
+
07 >= Read the status register.
The register is read by sending 07h via bulk out
and reading 64bytes via bulk in.
diff --git a/toprammer b/toprammer
index 6abc912..518d303 100755
--- a/toprammer
+++ b/toprammer
@@ -243,6 +243,10 @@ class TOP:
"""Read a byte from the FPGA data line into the status register."""
self.send("\x01")
+ def cmdFPGAWriteByte(self, byte):
+ """Write a byte to the FPGA data line."""
+ self.send("\x10" + chr(byte))
+
def cmdSetGNDPin(self, zifPin):
"""Assign GND to a ZIF socket pin. 0=none"""
valid = (0, 5, 14, 15, 16, 17, 18, 19, 20, 24, 26, 27,
bues.ch cgit interface