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authorMichael Buesch <mb@bu3sch.de>2010-01-31 23:01:56 +0100
committerMichael Buesch <mb@bu3sch.de>2010-01-31 23:01:56 +0100
commit85880258cc0ee4abcf4c4bcb00717b6277e0467c (patch)
treeea36d73ceb839280f03df6bc0da6edd8ac0697d0
parent1120e8e5ab03f843b4d64b17f86cbb7d317cc13f (diff)
downloadtoprammer-85880258cc0ee4abcf4c4bcb00717b6277e0467c.tar.xz
toprammer-85880258cc0ee4abcf4c4bcb00717b6277e0467c.zip
Document data fetching
Signed-off-by: Michael Buesch <mb@bu3sch.de>
-rw-r--r--chip_atmega8dip28.py48
-rw-r--r--reverse-engineering/HWPROTOCOL2
-rwxr-xr-xtoprammer10
3 files changed, 39 insertions, 21 deletions
diff --git a/chip_atmega8dip28.py b/chip_atmega8dip28.py
index 6d2cab1..3c6483c 100644
--- a/chip_atmega8dip28.py
+++ b/chip_atmega8dip28.py
@@ -146,6 +146,7 @@ class ATMega8DIP28(Chip):
image = ""
self.__setB1(1)
high = 0
+ self.top.blockCommands()
for chunk in range(0, 256, 2):
if chunk % 8 == 0:
percent = (chunk * 100 / 256)
@@ -153,7 +154,6 @@ class ATMega8DIP28(Chip):
self.printInfo("%d%%" % percent, newline=False)
else:
self.printInfo(".", newline=False)
- self.top.blockCommands()
self.top.send("\x34")
self.__setB1(0)
self.__setOE(1)
@@ -161,17 +161,11 @@ class ATMega8DIP28(Chip):
self.__loadAddrLow(chunk << 4)
self.__loadAddrHigh(high)
self.__setB1(1)
- self.top.unblockCommands()
for word in range(0, 31, 1):
value = (chunk << 4) + (word + 1)
high = (value >> 8) & 0xFF
- self.top.blockCommands()
- self.__setBS1(0)
- self.__setOE(0)
- self.top.send("\x01")
- self.__setBS1(1)
- self.top.send("\x01")
- self.__setOE(1)
+
+ self.__readWordToStatusReg()
self.__setB1(0)
self.top.send("\x34")
self.__setB1(0)
@@ -180,25 +174,42 @@ class ATMega8DIP28(Chip):
self.__loadAddrLow(value)
self.__loadAddrHigh(high)
self.__setB1(1)
- self.top.unblockCommands()
- self.top.blockCommands()
- self.__setBS1(0)
- self.__setOE(0)
- self.top.send("\x01")
- self.__setBS1(1)
- self.top.send("\x01")
- self.__setOE(1)
+ self.__readWordToStatusReg()
self.__setB1(0)
data = self.top.cmdReadStatusReg()
- self.top.unblockCommands()
image += data
+ self.top.unblockCommands()
self.printInfo("100%")
return image
def writeImage(self, image):
pass#TODO
+ def __readWordToStatusReg(self):
+ """Read a data word from the DUT into the status register."""
+ self.__setBS1(0)
+ self.__setOE(0)
+ self.top.cmdFPGAReadByte()
+ self.__setBS1(1)
+ self.top.cmdFPGAReadByte()
+ self.__setOE(1)
+
+ def __readLowByteToStatusReg(self):
+ """Read the low data byte from the DUT into the status register."""
+ self.__setBS1(0)
+ self.__setOE(0)
+ self.top.cmdFPGAReadByte()
+ self.__setOE(1)
+
+ def __readHighByteToStatusReg(self):
+ """Read the high data byte from the DUT into the status register."""
+ self.__setBS1(1)
+ self.__setOE(0)
+ self.top.cmdFPGAReadByte()
+ self.__setOE(1)
+
def __loadAddrLow(self, addrLow):
+ """Load the low address byte."""
self.__setBS1(0)
self.__setXA0(0)
self.__setXA1(0)
@@ -206,6 +217,7 @@ class ATMega8DIP28(Chip):
self.__pulseXTAL1()
def __loadAddrHigh(self, addrHigh):
+ """Load the high address byte."""
self.__setBS1(1)
self.__setXA0(0)
self.__setXA1(0)
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index 4a559e3..a28f348 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -6,6 +6,8 @@ TOP2049 USB protocol (incomplete)
00 >= NOP. No operation.
+01 >= Read a byte from the FPGA into the status register.
+
07 >= Read the status register.
The register is read by sending 07h via bulk out
and reading 64bytes via bulk in.
diff --git a/toprammer b/toprammer
index 2d14c04..6abc912 100755
--- a/toprammer
+++ b/toprammer
@@ -190,7 +190,7 @@ class TOP:
data = self.bitfile.getPayload()
for i in range(0, len(data), 60):
- self.cmdFPGAUploadData(data[i : i + 60])
+ self.cmdFPGAUploadConfig(data[i : i + 60])
def readImage(self):
"""Reads the chip image and returns it."""
@@ -232,13 +232,17 @@ class TOP:
"""Initiate a configuration sequence on the FPGA."""
self.send("\x0E\x21\x00\x00")
- def cmdFPGAUploadData(self, data):
- """Upload data into the FPGA."""
+ def cmdFPGAUploadConfig(self, data):
+ """Upload configuration data into the FPGA."""
assert(len(data) <= 60)
cmd = "\x0E\x22\x00\x00" + data
cmd += "\x00" * (64 - len(cmd)) # padding
self.send(cmd)
+ def cmdFPGAReadByte(self):
+ """Read a byte from the FPGA data line into the status register."""
+ self.send("\x01")
+
def cmdSetGNDPin(self, zifPin):
"""Assign GND to a ZIF socket pin. 0=none"""
valid = (0, 5, 14, 15, 16, 17, 18, 19, 20, 24, 26, 27,
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