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authorMichael Buesch <m@bues.ch>2012-04-07 00:03:34 +0200
committerMichael Buesch <m@bues.ch>2012-04-07 00:03:34 +0200
commit031078d37a6bc5b21c7ff5b16c972b2deb77a5ba (patch)
tree1e61fb591cb3740653ca06c460c3d2ebd5b84240 /README-DEVELOPERS.lyx
parent6c1ebab053c2e5264f561b88403ec03c6b03557d (diff)
downloadtoprammer-031078d37a6bc5b21c7ff5b16c972b2deb77a5ba.tar.xz
toprammer-031078d37a6bc5b21c7ff5b16c972b2deb77a5ba.zip
Rename libtoprammer/bit to libtoprammer/fpga
Signed-off-by: Michael Buesch <m@bues.ch>
Diffstat (limited to 'README-DEVELOPERS.lyx')
-rw-r--r--README-DEVELOPERS.lyx6
1 files changed, 3 insertions, 3 deletions
diff --git a/README-DEVELOPERS.lyx b/README-DEVELOPERS.lyx
index b86b675..4ee393a 100644
--- a/README-DEVELOPERS.lyx
+++ b/README-DEVELOPERS.lyx
@@ -658,7 +658,7 @@ http://www.xilinx.com/support/download/index.htm
\begin_layout Standard
To create a new sourcecode template fileset for a new chip, go to the libtopramm
-er/bit/src/ subdirectory and execute the "create.sh" script:
+er/fpga/src/ subdirectory and execute the "create.sh" script:
\end_layout
\begin_layout LyX-Code
@@ -668,9 +668,9 @@ er/bit/src/ subdirectory and execute the "create.sh" script:
\begin_layout Standard
Where "bitfile_name" is the name of the new chip's bitfile.
(That often matches the chip-ID).
- Now go to libtoprammer/bit/src/bitfile_name/ and implement the bottom-half
+ Now go to libtoprammer/fpga/src/bitfile_name/ and implement the bottom-half
algorithm in the bitfile_name.v Verilog file.
- To build the .BIT file from the Verilog sources, go to the libtoprammer/bit/
+ To build the .BIT file from the Verilog sources, go to the libtoprammer/fpga/
directory and execute:
\end_layout
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