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authorMichael Buesch <mb@bu3sch.de>2010-02-28 14:40:08 +0100
committerMichael Buesch <mb@bu3sch.de>2010-02-28 14:40:08 +0100
commit6dcf8ef4e89bdc135f8bd784b7972c6eab1f559c (patch)
tree366590f98ac80230a5d4354d5d9e48163b534368 /README-DEVELOPERS.lyx
parent3a4de0fc11ee7a6bbe561bbb1219f6e85412d2d3 (diff)
downloadtoprammer-6dcf8ef4e89bdc135f8bd784b7972c6eab1f559c.tar.xz
toprammer-6dcf8ef4e89bdc135f8bd784b7972c6eab1f559c.zip
More documentation
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Diffstat (limited to 'README-DEVELOPERS.lyx')
-rw-r--r--README-DEVELOPERS.lyx183
1 files changed, 182 insertions, 1 deletions
diff --git a/README-DEVELOPERS.lyx b/README-DEVELOPERS.lyx
index 10eb508..e99eb6f 100644
--- a/README-DEVELOPERS.lyx
+++ b/README-DEVELOPERS.lyx
@@ -33,6 +33,7 @@
\tracking_changes false
\output_changes false
\author ""
+\author ""
\end_header
\begin_body
@@ -510,12 +511,192 @@ supportedChips
supportedChips.append(Chip_MyDevice())
\end_layout
+\begin_layout Subsection
+FPGA bottom-half implementation
+\end_layout
+
+\begin_layout Standard
+For the FPGA part you need to get the Xilinx development suite (ISE) version
+ 9.2i.
+ It can be downloaded as "WebPACK" for free (as in beer) from the Xilinx
+ homepage in the "archive" section.
+\end_layout
+
+\begin_layout LyX-Code
+http://www.xilinx.com/support/download/i92linwp.htm
+\end_layout
+
+\begin_layout Standard
+To create a new sourcecode template fileset for a new chip, go to the libtopramm
+er/bit/src/ subdirectory and execute the "create.sh" script:
+\end_layout
+
+\begin_layout LyX-Code
+./create.sh name_of_chip
+\end_layout
+
+\begin_layout Standard
+Where "name_of_chip" is the name of the new chip.
+ Now go to libtoprammer/bit/src/name_of_chip/ and implement the bottom-half
+ algorithm in the name_of_chip.v Verilog file.
+ To build the .BIT file from the Verilog sources, go to the libtoprammer/bit/
+ directory and execute:
+\end_layout
+
+\begin_layout LyX-Code
+./build.sh name_of_chip
+\end_layout
+
+\begin_layout Standard
+(if you omit the chipname, all chips will be rebuilt).
+\end_layout
+
\begin_layout Section
Automatic layout generator
\end_layout
\begin_layout Standard
-TODO
+The automatic layout generator (layout_generator.py) can be used to automatically
+ generate a VCC/VPP/GND layout.
+ The generator will then tell you how to insert the chip into the ZIF socket.
+ The advantage of using the autogenerator instead of hardcoding the VCC/VPP/GND
+ connections in the chip implementation is that the autogenerated layout
+ is portable between TOPxxxx programmers and it is much easier to implement.
+ You do not have to search a chip position in the ZIF socket that fits the
+ device constraints.
+ The autogenerator will do it for you.
+\end_layout
+
+\begin_layout Standard
+The chip interface of the autogenerator is embedded into
+\begin_inset Quotes eld
+\end_inset
+
+class Chip
+\begin_inset Quotes erd
+\end_inset
+
+.
+ So you don't have to work with
+\begin_inset Quotes eld
+\end_inset
+
+class LayoutGenerator
+\begin_inset Quotes erd
+\end_inset
+
+ directly.
+ You'll do it through
+\begin_inset Quotes eld
+\end_inset
+
+class Chip
+\begin_inset Quotes erd
+\end_inset
+
+ instead.
+ So let's look at
+\begin_inset Quotes eld
+\end_inset
+
+class Chip
+\begin_inset Quotes erd
+\end_inset
+
+s autogenerator interface:
+\end_layout
+
+\begin_layout Standard
+The constructor (__init__()) has some autogenerator related parameters.
+\end_layout
+
+\begin_layout Description
+chipPackage This parameter is a string identifying the package type of the
+ DUT chip.
+ It is something like
+\begin_inset Quotes eld
+\end_inset
+
+DIP28
+\begin_inset Quotes erd
+\end_inset
+
+ or
+\begin_inset Quotes eld
+\end_inset
+
+DIP40
+\begin_inset Quotes erd
+\end_inset
+
+, etc...
+ .
+ If this parameter is passed to the constructor, the autogenerator is enabled.
+\end_layout
+
+\begin_layout Description
+chipPinVCCX This parameter is an integer specifying the VCC pin on the chip
+ package.
+ Note that it specifies the VCC pin on the chip package and _not_ on the
+ ZIF socket.
+ So if your chip datasheet tells you that VCC is on pin 8, you pass an 8
+ here.
+\end_layout
+
+\begin_layout Description
+chipPinsVPP This parameter is an integer or a list of integers specifying
+ the VPP pin(s) on the chip package.
+ Note that it specifies the VCC pin on the chip package and _not_ on the
+ ZIF socket.
+ So if your chip datasheet tells you that VCC is on pin 1, you pass an 1
+ here.
+ If your chip needs multiple VPP voltages, just pass a list of pins.
+\end_layout
+
+\begin_layout Description
+chipPinGND This parameter is an integer specifying the GND pin on the chip
+ package.
+ Note that it specifies the VCC pin on the chip package and _not_ on the
+ ZIF socket.
+ So if your chip datasheet tells you that VCC is on pin 5, you pass an 5
+ here.
+\end_layout
+
+\begin_layout Standard
+After passing all parameters to the
+\begin_inset Quotes eld
+\end_inset
+
+class Chip
+\begin_inset Quotes erd
+\end_inset
+
+ constructor, the autogenerator is initialized and ready to be used.
+ The following methods can be used to apply or disable a layout:
+\end_layout
+
+\begin_layout Description
+applyVCCX(on) This method enables or disables (depending on the parameter)
+ a layout.
+ Enabling the layout means that the VCCX pin will be actively driven by
+ the configured VCCX voltage.
+ Disabling the layout will tristate the driver.
+\end_layout
+
+\begin_layout Description
+applyVPP(on) This method enables or disables (depending on the parameter)
+ a layout.
+ Enabling the layout means that the VPP pins will be actively driven by
+ the configured VPP voltage.
+ Disabling the layout will tristate the driver.
+\end_layout
+
+\begin_layout Description
+applyGND(on) This method enables or disables (depending on the parameter)
+ a layout.
+ Enabling the layout means that the GND pins will be actively driven by
+ GND.
+ Disabling the layout will tristate the driver.
\end_layout
\end_body
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