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authorMichael Buesch <mb@bu3sch.de>2011-01-08 23:21:55 +0100
committerMichael Buesch <mb@bu3sch.de>2011-01-08 23:21:55 +0100
commit0b71654c22a3da3747e2306961f05d5367c2de30 (patch)
tree6b36de27a4d05655974ed72ff146c82f64c4a24f /reverse-engineering
parenteb9de8d8a075211638d5a4b1c433855bb41be610 (diff)
downloadtoprammer-0b71654c22a3da3747e2306961f05d5367c2de30.tar.xz
toprammer-0b71654c22a3da3747e2306961f05d5367c2de30.zip
Unify the FPGA read API
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Diffstat (limited to 'reverse-engineering')
-rw-r--r--reverse-engineering/HWPROTOCOL2
-rwxr-xr-xreverse-engineering/dump-parser.py15
2 files changed, 11 insertions, 6 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index 8af0aa9..c7dd25b 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -54,6 +54,8 @@ TOP2049 USB protocol (incomplete)
0E220000... >= Program the FPGA. 60bytes of data is appended.
+0E28xx00 >= Enable signals on the ZIF socket. 0->enable 1->disable
+
10xx >= Write a byte (xx) to the FPGA at address 0x10.
19 >= Unknown
diff --git a/reverse-engineering/dump-parser.py b/reverse-engineering/dump-parser.py
index b2f9e3d..81ec1bd 100755
--- a/reverse-engineering/dump-parser.py
+++ b/reverse-engineering/dump-parser.py
@@ -62,18 +62,18 @@ def dumpInstr(instr, description):
def parseBulkIn(data):
if len(data) == 64:
- print "Read status register"
+ print "Read buffer register"
dumpMem(data)
def parseBulkOut(data):
i = 0
while i < len(data):
if data[i] == 0x00:
- dumpInstr(data[i:i+1], "NOP")
+ dumpInstr(data[i:i+1], "Delay 4 usec")
elif data[i] == 0x01:
dumpInstr(data[i:i+1], "Read byte from FPGA")
elif data[i] == 0x07:
- dumpInstr(data[i:i+1], "Read status register request")
+ dumpInstr(data[i:i+1], "Read buffer register request")
elif data[i] == 0x0A:
dumpInstr(data[i:i+3], "Write 0x%02X to the FPGA at address 0x%02X" % (data[i+2], data[i+1]))
i += 2
@@ -113,7 +113,10 @@ def parseBulkOut(data):
dumpInstr(data[i:i+4], "Unknown 0x0E25")
i += 3
elif data[i] == 0x0E and data[i+1] == 0x28:
- dumpInstr(data[i:i+4], "Unknown 0x0E28")
+ op = "Disable"
+ if data[i+2] == chr(0):
+ op = "Enable"
+ dumpInstr(data[i:i+4], "%s the ZIF socket" % op)
i += 3
elif data[i] == 0x0E and data[i+1] == 0x1F:
dumpInstr(data[i:i+4], "Unknown 0x0E1F")
@@ -121,12 +124,12 @@ def parseBulkOut(data):
elif data[i] == 0x0D:
dumpInstr(data[i:i+1], "Unknown 0x0D")
elif data[i] == 0x10:
- dumpInstr(data[i:i+2], "Write 0x%02X to the FPGA" % data[i+1])
+ dumpInstr(data[i:i+2], "Write 0x%02X to the FPGA at address 0x10" % data[i+1])
i += 1
elif data[i] == 0x19:
dumpInstr(data[i:i+1], "Unknown 0x19")
elif data[i] == 0x1B:
- dumpInstr(data[i:i+1], "Flush request")
+ dumpInstr(data[i:i+1], "Delay 10 msec")
elif data[i] == 0x34:
dumpInstr(data[i:i+1], "Unknown 0x34")
elif data[i] == 0x38:
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