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authorMichael Buesch <mb@bu3sch.de>2010-01-31 23:05:55 +0100
committerMichael Buesch <mb@bu3sch.de>2010-01-31 23:05:55 +0100
commit81743dc1458f5ba6161a9c6161884aa9df021a71 (patch)
tree4b6ffa72ed01fb353ec420d36b218e1c1e3919d9 /reverse-engineering
parent85880258cc0ee4abcf4c4bcb00717b6277e0467c (diff)
downloadtoprammer-81743dc1458f5ba6161a9c6161884aa9df021a71.tar.xz
toprammer-81743dc1458f5ba6161a9c6161884aa9df021a71.zip
Document FPGA data writing
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Diffstat (limited to 'reverse-engineering')
-rw-r--r--reverse-engineering/HWPROTOCOL2
1 files changed, 2 insertions, 0 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index a28f348..938a7b8 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -8,6 +8,8 @@ TOP2049 USB protocol (incomplete)
01 >= Read a byte from the FPGA into the status register.
+10xx >= Write a byte (xx) to the FPGA.
+
07 >= Read the status register.
The register is read by sending 07h via bulk out
and reading 64bytes via bulk in.
bues.ch cgit interface