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authorMichael Buesch <mb@bu3sch.de>2010-01-31 23:01:56 +0100
committerMichael Buesch <mb@bu3sch.de>2010-01-31 23:01:56 +0100
commit85880258cc0ee4abcf4c4bcb00717b6277e0467c (patch)
treeea36d73ceb839280f03df6bc0da6edd8ac0697d0 /reverse-engineering
parent1120e8e5ab03f843b4d64b17f86cbb7d317cc13f (diff)
downloadtoprammer-85880258cc0ee4abcf4c4bcb00717b6277e0467c.tar.xz
toprammer-85880258cc0ee4abcf4c4bcb00717b6277e0467c.zip
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Signed-off-by: Michael Buesch <mb@bu3sch.de>
Diffstat (limited to 'reverse-engineering')
-rw-r--r--reverse-engineering/HWPROTOCOL2
1 files changed, 2 insertions, 0 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index 4a559e3..a28f348 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -6,6 +6,8 @@ TOP2049 USB protocol (incomplete)
00 >= NOP. No operation.
+01 >= Read a byte from the FPGA into the status register.
+
07 >= Read the status register.
The register is read by sending 07h via bulk out
and reading 64bytes via bulk in.
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