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authorMichael Buesch <m@bues.ch>2012-04-06 21:32:42 +0200
committerMichael Buesch <m@bues.ch>2012-04-06 21:32:42 +0200
commit889ae3e0f47de1bf4ba9e3ef13e139e4f18b5143 (patch)
treeb7b1d7967b4c1e3c04e2328f4806e5197ae3d4b7 /reverse-engineering
parent17b6325db3704c756e107342f281bf3ac0a32e41 (diff)
downloadtoprammer-889ae3e0f47de1bf4ba9e3ef13e139e4f18b5143.tar.xz
toprammer-889ae3e0f47de1bf4ba9e3ef13e139e4f18b5143.zip
Rename VCCX to VCC
Signed-off-by: Michael Buesch <m@bues.ch>
Diffstat (limited to 'reverse-engineering')
-rw-r--r--reverse-engineering/HWPROTOCOL4
-rwxr-xr-xreverse-engineering/dump-parser.py4
-rw-r--r--reverse-engineering/vccx-sniffer.patch4
3 files changed, 6 insertions, 6 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index c912cfd..8393133 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -26,7 +26,7 @@ TOP2049 USB protocol (incomplete)
0E12xx00 >= Set VPP, where xx is the voltage.
xx is in centivolt.
-0E13xx00 >= Set VCCX, where xx is the voltage.
+0E13xx00 >= Set VCC, where xx is the voltage.
xx is in centivolt.
0E14xx00 >= Load the ZIF socket VPP supply layout.
@@ -34,7 +34,7 @@ TOP2049 USB protocol (incomplete)
(Shift data into the 4 shiftregisters on the left side.
Sends 4 times 8 clock pulses and one strobe.)
-0E15xx00 >= Load the ZIF socket VCCX supply layout.
+0E15xx00 >= Load the ZIF socket VCC supply layout.
xx is the layout ID.
(Shift data into the 3 shiftregisters on the right side.
Sends 3 times 8 clock pulses and one strobe.)
diff --git a/reverse-engineering/dump-parser.py b/reverse-engineering/dump-parser.py
index 7fadcd0..85735f0 100755
--- a/reverse-engineering/dump-parser.py
+++ b/reverse-engineering/dump-parser.py
@@ -89,13 +89,13 @@ def parseBulkOut(data):
i += 3
elif data[i] == 0x0E and data[i+1] == 0x13:
centivolts = data[i+2]
- dumpInstr(data[i:i+4], "Set VCCX to %.2f Volts" % (float(centivolts) / 10))
+ dumpInstr(data[i:i+4], "Set VCC to %.2f Volts" % (float(centivolts) / 10))
i += 3
elif data[i] == 0x0E and data[i+1] == 0x14:
dumpInstr(data[i:i+4], "Loading VPP layout %d" % data[i+1])
i += 3
elif data[i] == 0x0E and data[i+1] == 0x15:
- dumpInstr(data[i:i+4], "Loading VCCX layout %d" % data[i+1])
+ dumpInstr(data[i:i+4], "Loading VCC layout %d" % data[i+1])
i += 3
elif data[i] == 0x0E and data[i+1] == 0x16:
dumpInstr(data[i:i+4], "Loading GND layout %d" % data[i+1])
diff --git a/reverse-engineering/vccx-sniffer.patch b/reverse-engineering/vccx-sniffer.patch
index c5b7c75..79b2b51 100644
--- a/reverse-engineering/vccx-sniffer.patch
+++ b/reverse-engineering/vccx-sniffer.patch
@@ -17,8 +17,8 @@ index 3962d44..4b00100 100644
+ s = hc4094sniffer.Sniffer("/dev/ttyUSB0", 3)
+ count = 0
+ for i in range(0, 0xFF+1):
-+ self.cmdLoadVCCXLayout(0)
-+ self.cmdLoadVCCXLayout(i)
++ self.cmdLoadVCCLayout(0)
++ self.cmdLoadVCCLayout(i)
+ self.flushCommands()
+ time.sleep(0.1)
+ d = s.read()
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