path: root/reverse-engineering
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authorMichael Buesch <>2010-02-07 01:10:33 +0100
committerMichael Buesch <>2010-02-07 01:10:33 +0100
commit8c78271b641ebfbb0b0a4df0a7a0bdc619bbfb26 (patch)
treee8a5efca46a400ce1f8f98a8a0328314032a3b31 /reverse-engineering
parent6317ae834292f9a935b749229bf3b6eec07bbc20 (diff)
Document FPGA parallel interface access
Signed-off-by: Michael Buesch <>
Diffstat (limited to 'reverse-engineering')
1 files changed, 4 insertions, 0 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index 938a7b8..a7c47b7 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -14,6 +14,10 @@ TOP2049 USB protocol (incomplete)
The register is read by sending 07h via bulk out
and reading 64bytes via bulk in.
+0Axxyy >= Write data into the FPGA via the parallel uc->FPGA interface.
+ xx is the address (clocked via ALE).
+ yy is the data (clocked via WR).
0E110000 >= Put the device ID string into the status register.
String length is 16 bytes. cgit interface