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authorMichael Buesch <mb@bu3sch.de>2011-01-08 22:50:07 +0100
committerMichael Buesch <mb@bu3sch.de>2011-01-08 22:50:07 +0100
commitd52ba369193baed9abd135d0afbd69be84841c85 (patch)
treec951fed31410531beb79d7fb92cb3b071b98acef /reverse-engineering
parent2db507b4eccbd4fad34e156a5a72ace417a9af17 (diff)
downloadtoprammer-d52ba369193baed9abd135d0afbd69be84841c85.tar.xz
toprammer-d52ba369193baed9abd135d0afbd69be84841c85.zip
Rewrite delay mechanisms
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Diffstat (limited to 'reverse-engineering')
-rw-r--r--reverse-engineering/HWPROTOCOL4
1 files changed, 2 insertions, 2 deletions
diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
index 6e01228..8af0aa9 100644
--- a/reverse-engineering/HWPROTOCOL
+++ b/reverse-engineering/HWPROTOCOL
@@ -4,7 +4,7 @@ TOP2049 USB protocol (incomplete)
=== COMMANDS ===
-00 >= NOP. No operation.
+00 >= 4 usec delay
01 >= Read a byte from the FPGA at address 0x10 into the status register.
@@ -58,7 +58,7 @@ TOP2049 USB protocol (incomplete)
19 >= Unknown
-1B >= Flush (and/or commit) command
+1B >= 10 msec delay
34 >= Unknown
bues.ch cgit interface