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-rw-r--r--libtoprammer/fpga/common/common.vh46
-rw-r--r--libtoprammer/fpga/src/_27cxxxdip28/_27cxxxdip28.v4
-rw-r--r--libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v4
-rw-r--r--libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v4
-rw-r--r--libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v4
-rw-r--r--libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v2
-rw-r--r--libtoprammer/fpga/src/microchip01/microchip01.vh4
-rw-r--r--libtoprammer/fpga/src/microchip16/microchip16.vh4
-rw-r--r--libtoprammer/fpga/src/template/template.v100
-rw-r--r--libtoprammer/fpga/src/unitest/unitest.v2
-rw-r--r--libtoprammer/fpga/src/unitest_fcnt/unitest_fcnt.v2
11 files changed, 104 insertions, 72 deletions
diff --git a/libtoprammer/fpga/common/common.vh b/libtoprammer/fpga/common/common.vh
index 957afa7..b2fe3d2 100644
--- a/libtoprammer/fpga/common/common.vh
+++ b/libtoprammer/fpga/common/common.vh
@@ -70,15 +70,6 @@
/** BOTTOMHALF_END - End bottom-half module */
`define BOTTOMHALF_END \
- initial begin \
- __addr_latch <= 0; \
- out_data <= 0; \
- __delay_count <= 0; \
- __cmd_running <= 0; \
- __cmd <= 0; \
- __cmd_state <= 0; \
- end \
- \
always @(negedge __ale_signal) begin \
__addr_latch <= __data; \
end \
@@ -96,6 +87,25 @@
bufif0(__data[7], out_data[7], !__data_oe); \
endmodule
+/** INITIAL_BEGIN - Begin initialization section. */
+`define INITIAL_BEGIN \
+ initial begin \
+ __addr_latch <= 0; \
+ out_data <= 0; \
+ __delay_count <= 0; \
+ __cmd_running <= 0; \
+ __cmd <= 0; \
+ __cmd_state <= 0;
+
+/** INITIAL_END - End initialization section. */
+`define INITIAL_END \
+ end /* initial */
+
+/** INITIAL_NONE - Defines a dummy initial section. */
+`define INITIAL_NONE \
+ `INITIAL_BEGIN \
+ `INITIAL_END
+
/** ASYNCPROC_BEGIN - Begin asynchronous OSC-based processing section. */
`define ASYNCPROC_BEGIN \
always @(posedge osc_signal) begin \
@@ -148,12 +158,28 @@
endcase \
end /* always */
+/** ZIF_BUF0 - Declare a ZIF buffer with negative outen.
+ * @PIN: The pin number.
+ * @OUT: The output signal.
+ * @NOUTEN: The output enable signal, active low.
+ */
+`define ZIF_BUF0(PIN, OUT, NOUTEN) \
+ bufif0(zif[PIN], OUT, NOUTEN);
+
+/** ZIF_BUF1 - Declare a ZIF buffer with positive outen.
+ * @PIN: The pin number.
+ * @OUT: The output signal.
+ * @OUTEN: The output enable signal, active high.
+ */
+`define ZIF_BUF1(PIN, OUT, OUTEN) \
+ bufif1(zif[PIN], OUT, OUTEN);
+
/** ZIF_UNUSED - Declare a ZIF pin as unused.
* @PIN: The pin number.
* The ZIF pin is tied low.
*/
`define ZIF_UNUSED(PIN) \
- bufif0(zif[PIN], low, low);
+ `ZIF_BUF0(PIN, low, low)
/** CMD_RUN - Run a command.
* @NR: The command number.
diff --git a/libtoprammer/fpga/src/_27cxxxdip28/_27cxxxdip28.v b/libtoprammer/fpga/src/_27cxxxdip28/_27cxxxdip28.v
index 7d293a7..121aba5 100644
--- a/libtoprammer/fpga/src/_27cxxxdip28/_27cxxxdip28.v
+++ b/libtoprammer/fpga/src/_27cxxxdip28/_27cxxxdip28.v
@@ -51,7 +51,7 @@
`define CMD_PPULSE 0
- initial begin
+ `INITIAL_BEGIN
cdata <= 0;
cdata_en <= 0;
caddr <= 0;
@@ -62,7 +62,7 @@
prog_en <= 0;
oe <= 1;
ctype <= 0;
- end
+ `INITIAL_END
wire prog_pulse;
assign prog_pulse = prog_en ? prog_pulse_reg : high;
diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v
index f80e438..fb37d7e 100644
--- a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v
+++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v
@@ -33,7 +33,7 @@
reg dut_vcc_en;
reg dut_vcc;
- initial begin
+ `INITIAL_BEGIN
dut_oe <= 0;
dut_wr <= 0;
dut_xtal <= 0;
@@ -47,7 +47,7 @@
dut_vpp <= 0;
dut_vcc_en <= 0;
dut_vcc <= 0;
- end
+ `INITIAL_END
`ASYNCPROC_NONE
diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v
index 857815c..f772a5c 100644
--- a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v
+++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v
@@ -34,7 +34,7 @@
reg vcc_en;
reg vcc;
- initial begin
+ `INITIAL_BEGIN
oe <= 0;
wr <= 0;
xtal <= 0;
@@ -48,7 +48,7 @@
vpp <= 0;
vcc_en <= 0;
vcc <= 0;
- end
+ `INITIAL_END
`ASYNCPROC_NONE
diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v
index f4cd419..ff89d81 100644
--- a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v
+++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v
@@ -41,7 +41,7 @@
reg [10:0] sii_buf;
reg [10:0] sdo_buf;
- initial begin
+ `INITIAL_BEGIN
prog_count <= 0;
dut_sdi <= 0;
dut_sii <= 0;
@@ -54,7 +54,7 @@
sdi_buf <= 0;
sii_buf <= 0;
sdo_buf <= 0;
- end
+ `INITIAL_END
`ASYNCPROC_BEGIN
if (`CMD_IS(`CMD_SENDINSTR)) begin
diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v
index 835706c..4ceb000 100644
--- a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v
+++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v
@@ -30,6 +30,8 @@
reg dut_oe;
reg dut_we;
+ `INITIAL_NONE
+
`ASYNCPROC_NONE
`DATAWRITE_BEGIN
diff --git a/libtoprammer/fpga/src/microchip01/microchip01.vh b/libtoprammer/fpga/src/microchip01/microchip01.vh
index a1ee767..faeb4d8 100644
--- a/libtoprammer/fpga/src/microchip01/microchip01.vh
+++ b/libtoprammer/fpga/src/microchip01/microchip01.vh
@@ -51,7 +51,7 @@
reg sdio_auto; \
wire is_command; \
\
- initial begin \
+ `INITIAL_BEGIN \
prog_count <= 0; \
dut_sci_manual <= 0; \
dut_sci_auto <= 0; \
@@ -66,7 +66,7 @@
tdly <= 24; \
dly5 <= 5; \
sdio_auto <= 1; \
- end \
+ `INITIAL_END \
\
`ASYNCPROC_BEGIN \
if (`CMD_IS_RUNNING) begin \
diff --git a/libtoprammer/fpga/src/microchip16/microchip16.vh b/libtoprammer/fpga/src/microchip16/microchip16.vh
index ce6b51c..4471356 100644
--- a/libtoprammer/fpga/src/microchip16/microchip16.vh
+++ b/libtoprammer/fpga/src/microchip16/microchip16.vh
@@ -54,7 +54,7 @@
reg [3:0] dly5; \
reg [7:0] tdly; \
\
- initial begin \
+ `INITIAL_BEGIN \
prog_count <= 0; \
dut_sci_manual <= 0; \
dut_sci_auto <= 0; \
@@ -69,7 +69,7 @@
enterpm_seq <= `ENTERPM_SEQ ;\
tdly <= 24; \
dly5 <= 5; \
- end \
+ `INITIAL_END \
\
`ASYNCPROC_BEGIN \
if (`CMD_IS_RUNNING) begin \
diff --git a/libtoprammer/fpga/src/template/template.v b/libtoprammer/fpga/src/template/template.v
index a464350..f8b5496 100644
--- a/libtoprammer/fpga/src/template/template.v
+++ b/libtoprammer/fpga/src/template/template.v
@@ -26,9 +26,9 @@
`BOTTOMHALF_BEGIN(template, 16'hCAFE, 42) /* TODO: <<< Adjust IDs here */
reg examplereg;
- initial begin
+ `INITIAL_BEGIN
examplereg <= 0;
- end
+ `INITIAL_END
`ASYNCPROC_BEGIN
/* TODO */
@@ -51,52 +51,52 @@
end
`DATAREAD_END
- bufif0(zif[1], examplereg, low);
- bufif0(zif[2], low, low);
- bufif0(zif[3], low, low);
- bufif0(zif[4], low, low);
- bufif0(zif[5], low, low);
- bufif0(zif[6], low, low);
- bufif0(zif[7], low, low);
- bufif0(zif[8], low, low);
- bufif0(zif[9], low, low);
- bufif0(zif[10], low, low);
- bufif0(zif[11], low, low);
- bufif0(zif[12], low, low);
- bufif0(zif[13], low, low);
- bufif0(zif[14], low, low);
- bufif0(zif[15], low, low);
- bufif0(zif[16], low, low);
- bufif0(zif[17], low, low);
- bufif0(zif[18], low, low);
- bufif0(zif[19], low, low);
- bufif0(zif[20], low, low);
- bufif0(zif[21], low, low);
- bufif0(zif[22], low, low);
- bufif0(zif[23], low, low);
- bufif0(zif[24], low, low);
- bufif0(zif[25], low, low);
- bufif0(zif[26], low, low);
- bufif0(zif[27], low, low);
- bufif0(zif[28], low, low);
- bufif0(zif[29], low, low);
- bufif0(zif[30], low, low);
- bufif0(zif[31], low, low);
- bufif0(zif[32], low, low);
- bufif0(zif[33], low, low);
- bufif0(zif[34], low, low);
- bufif0(zif[35], low, low);
- bufif0(zif[36], low, low);
- bufif0(zif[37], low, low);
- bufif0(zif[38], low, low);
- bufif0(zif[39], low, low);
- bufif0(zif[40], low, low);
- bufif0(zif[41], low, low);
- bufif0(zif[42], low, low);
- bufif0(zif[43], low, low);
- bufif0(zif[44], low, low);
- bufif0(zif[45], low, low);
- bufif0(zif[46], low, low);
- bufif0(zif[47], low, low);
- bufif0(zif[48], low, low);
+ `ZIF_BUF0(1, examplereg, low);
+ `ZIF_BUF0(2, low, low);
+ `ZIF_BUF0(3, low, low);
+ `ZIF_BUF0(4, low, low);
+ `ZIF_BUF0(5, low, low);
+ `ZIF_BUF0(6, low, low);
+ `ZIF_BUF0(7, low, low);
+ `ZIF_BUF0(8, low, low);
+ `ZIF_BUF0(9, low, low);
+ `ZIF_BUF0(10, low, low);
+ `ZIF_BUF0(11, low, low);
+ `ZIF_BUF0(12, low, low);
+ `ZIF_BUF0(13, low, low);
+ `ZIF_BUF0(14, low, low);
+ `ZIF_BUF0(15, low, low);
+ `ZIF_BUF0(16, low, low);
+ `ZIF_BUF0(17, low, low);
+ `ZIF_BUF0(18, low, low);
+ `ZIF_BUF0(19, low, low);
+ `ZIF_BUF0(20, low, low);
+ `ZIF_BUF0(21, low, low);
+ `ZIF_BUF0(22, low, low);
+ `ZIF_BUF0(23, low, low);
+ `ZIF_BUF0(24, low, low);
+ `ZIF_BUF0(25, low, low);
+ `ZIF_BUF0(26, low, low);
+ `ZIF_BUF0(27, low, low);
+ `ZIF_BUF0(28, low, low);
+ `ZIF_BUF0(29, low, low);
+ `ZIF_BUF0(30, low, low);
+ `ZIF_BUF0(31, low, low);
+ `ZIF_BUF0(32, low, low);
+ `ZIF_BUF0(33, low, low);
+ `ZIF_BUF0(34, low, low);
+ `ZIF_BUF0(35, low, low);
+ `ZIF_BUF0(36, low, low);
+ `ZIF_BUF0(37, low, low);
+ `ZIF_BUF0(38, low, low);
+ `ZIF_BUF0(39, low, low);
+ `ZIF_BUF0(40, low, low);
+ `ZIF_BUF0(41, low, low);
+ `ZIF_BUF0(42, low, low);
+ `ZIF_BUF0(43, low, low);
+ `ZIF_BUF0(44, low, low);
+ `ZIF_BUF0(45, low, low);
+ `ZIF_BUF0(46, low, low);
+ `ZIF_BUF0(47, low, low);
+ `ZIF_BUF0(48, low, low);
`BOTTOMHALF_END
diff --git a/libtoprammer/fpga/src/unitest/unitest.v b/libtoprammer/fpga/src/unitest/unitest.v
index 78f50c9..0f81ec2 100644
--- a/libtoprammer/fpga/src/unitest/unitest.v
+++ b/libtoprammer/fpga/src/unitest/unitest.v
@@ -32,6 +32,8 @@
reg [23:0] osc_divider;
reg [23:0] osc_div_cnt;
+ `INITIAL_NONE
+
always @(posedge osc_signal) begin
if (osc_div_cnt + 1 >= osc_divider) begin
osc_div_cnt <= 0;
diff --git a/libtoprammer/fpga/src/unitest_fcnt/unitest_fcnt.v b/libtoprammer/fpga/src/unitest_fcnt/unitest_fcnt.v
index a3b4b95..04b3c41 100644
--- a/libtoprammer/fpga/src/unitest_fcnt/unitest_fcnt.v
+++ b/libtoprammer/fpga/src/unitest_fcnt/unitest_fcnt.v
@@ -39,6 +39,8 @@
reg [27:0] fcnt_count;
reg [27:0] fcnt_saved_count;
+ `INITIAL_NONE
+
always @(posedge osc_signal) begin
if (osc_div_cnt + 1 >= osc_divider) begin
osc_div_cnt <= 0;
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