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-rw-r--r--chip_atmega8dip28.py19
-rwxr-xr-xtoprammer11
2 files changed, 18 insertions, 12 deletions
diff --git a/chip_atmega8dip28.py b/chip_atmega8dip28.py
index 0b22e85..1a9364f 100644
--- a/chip_atmega8dip28.py
+++ b/chip_atmega8dip28.py
@@ -175,16 +175,17 @@ class ATMega8DIP28(Chip):
self.top.blockCommands()
self.top.cmdFlush(2)
- self.top.send("\x0B\x16")
- self.top.send("\x0B\x17")
- self.top.send("\x0B\x18")
- self.top.send("\x0B\x19")
- self.top.send("\x0B\x1A")
- self.top.send("\x0B\x1B")
- stat = self.top.cmdReadStatusReg32()
+ self.top.cmdFPGAReadRaw(0x16)
+ self.top.cmdFPGAReadRaw(0x17)
+ self.top.cmdFPGAReadRaw(0x18)
+ self.top.cmdFPGAReadRaw(0x19)
+ self.top.cmdFPGAReadRaw(0x1A)
+ self.top.cmdFPGAReadRaw(0x1B)
+ stat = self.top.cmdReadStatusReg48()
self.top.unblockCommands()
- if stat != 0xFFFFFFC0:
- msg = "Did not detect chip. Please check connections. (0x%08X)" % stat
+ if stat != 0x0303FFFFFFC0 and \
+ (stat & 0x00FFFFFFFFFF) != 0x00031F800000:
+ msg = "Did not detect chip. Please check connections. (0x%012X)" % stat
if self.top.getForceLevel() >= 2:
self.printWarning(msg)
else:
diff --git a/toprammer b/toprammer
index 5169cf3..f24a9af 100755
--- a/toprammer
+++ b/toprammer
@@ -158,7 +158,7 @@ class TOP:
if stat != 0x00020C69:
raise TOPException("Init: Unexpected status register (a): 0x%08X" % stat)
- self.send("\x0A\x1B\xFF")
+ self.cmdFPGAWrite(0x1B, 0xFF)
self.cmdSetVPPVoltage(0)
self.cmdFlush()
self.cmdSetVPPVoltage(0)
@@ -171,7 +171,7 @@ class TOP:
self.cmdFlush()
self.cmdSetVCCXVoltage(0)
self.cmdFlush()
- self.send("\x0A\x1D\x86")
+ self.cmdFPGAWrite(0x1D, 0x86)
self.cmdSetGNDPin(0)
self.cmdLoadVPPLayout(0)
self.cmdLoadVCCXLayout(0)
@@ -193,7 +193,7 @@ class TOP:
def __bitfileUpload(self):
self.printDebug("Uploading bitfile...")
- self.send("\x0A\x1B\x00")
+ self.cmdFPGAWrite(0x1B, 0x00)
self.cmdFPGAInitiateConfig()
stat = self.cmdReadStatusReg32()
if stat != 0x00006801:
@@ -301,6 +301,11 @@ class TOP:
"""Read a byte from the FPGA data line into the status register."""
self.send("\x01")
+ def cmdFPGAReadRaw(self, address):
+ """Read a byte from the FPGA at address into the status register."""
+ cmd = chr(0x0B) + chr(address)
+ self.send(cmd)
+
def cmdFPGAWrite(self, address, byte):
"""Write a byte to an FPGA address."""
cmd = chr(0x0A) + chr(address) + chr(byte)
bues.ch cgit interface