From 031078d37a6bc5b21c7ff5b16c972b2deb77a5ba Mon Sep 17 00:00:00 2001 From: Michael Buesch Date: Sat, 7 Apr 2012 00:03:34 +0200 Subject: Rename libtoprammer/bit to libtoprammer/fpga Signed-off-by: Michael Buesch --- README-DEVELOPERS.lyx | 6 +- README-DEVELOPERS.ps | 160 +++---- libtoprammer/bit/.gitignore | 1 - libtoprammer/bit/at27c256r.bit | Bin 24786 -> 0 bytes libtoprammer/bit/at89c2051dip20.bit | Bin 24791 -> 0 bytes libtoprammer/bit/atmega32dip40.bit | Bin 24790 -> 0 bytes libtoprammer/bit/atmega8dip28.bit | Bin 24789 -> 0 bytes libtoprammer/bit/attiny13dip8.bit | Bin 24789 -> 0 bytes libtoprammer/bit/attiny26dip20.bit | Bin 24790 -> 0 bytes libtoprammer/bit/build.sh | 118 ----- libtoprammer/bit/hm62256dip28.bit | Bin 24789 -> 0 bytes libtoprammer/bit/m24c16dip8.bit | Bin 24787 -> 0 bytes libtoprammer/bit/m2764a.bit | Bin 24783 -> 0 bytes libtoprammer/bit/m8c-issp.bit | Bin 24785 -> 0 bytes libtoprammer/bit/src/.gitignore | 29 -- libtoprammer/bit/src/at27c256r/Makefile | 4 - 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libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.xst create mode 100644 libtoprammer/fpga/unitest.bit create mode 100644 libtoprammer/fpga/w29ee011dip32.bit diff --git a/README-DEVELOPERS.lyx b/README-DEVELOPERS.lyx index b86b675..4ee393a 100644 --- a/README-DEVELOPERS.lyx +++ b/README-DEVELOPERS.lyx @@ -658,7 +658,7 @@ http://www.xilinx.com/support/download/index.htm \begin_layout Standard To create a new sourcecode template fileset for a new chip, go to the libtopramm -er/bit/src/ subdirectory and execute the "create.sh" script: +er/fpga/src/ subdirectory and execute the "create.sh" script: \end_layout \begin_layout LyX-Code @@ -668,9 +668,9 @@ er/bit/src/ subdirectory and execute the "create.sh" script: \begin_layout Standard Where "bitfile_name" is the name of the new chip's bitfile. (That often matches the chip-ID). - Now go to libtoprammer/bit/src/bitfile_name/ and implement the bottom-half + Now go to libtoprammer/fpga/src/bitfile_name/ and implement the bottom-half algorithm in the bitfile_name.v Verilog file. - To build the .BIT file from the Verilog sources, go to the libtoprammer/bit/ + To build the .BIT file from the Verilog sources, go to the libtoprammer/fpga/ directory and execute: \end_layout diff --git a/README-DEVELOPERS.ps b/README-DEVELOPERS.ps index 50491ee..a00237d 100644 --- a/README-DEVELOPERS.ps +++ b/README-DEVELOPERS.ps @@ -1,7 +1,7 @@ %!PS-Adobe-2.0 %%Creator: dvips(k) 5.991 Copyright 2011 Radical Eye Software %%Title: README-DEVELOPERS.dvi -%%CreationDate: Fri Apr 6 23:26:54 2012 +%%CreationDate: Sat Apr 7 00:00:34 2012 %%Pages: 7 %%PageOrder: Ascend %%BoundingBox: 0 0 612 792 @@ -11,7 +11,7 @@ %DVIPSWebPage: (www.radicaleye.com) %DVIPSCommandLine: dvips -o README-DEVELOPERS.ps README-DEVELOPERS.dvi %DVIPSParameters: dpi=600 -%DVIPSSource: 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4407 +b(.)39 b(Y)-7 b(ou'll)28 b(do)g(it)h(through)515 4507 y(\020class)d(Chip\021)34 b(instead.)j(So)27 b(let's)h(lo)r(ok)f(at)g (\020class)g(Chip\021s)g(autogenerator)e(in)n(terface.)639 -4507 y(The)j(constructor)e(\(__init__\(\)\))h(has)g(some)g -(autogenerator)e(related)i(parameters:)515 4673 y Fe(c)m(hipP)m(ac)m(k) +4607 y(The)j(constructor)e(\(__init__\(\)\))h(has)g(some)g +(autogenerator)e(related)i(parameters:)515 4773 y Fe(c)m(hipP)m(ac)m(k) -5 b(age)43 b Fd(This)36 b(parameter)e(is)i(a)f(string)h(iden)n (tifying)g(the)g(pac)n(k)-5 b(age)34 b(t)n(yp)r(e)i(of)g(the)722 -4773 y(DUT)26 b(c)n(hip.)36 b(It)25 b(is)g(something)g(lik)n(e)f +4872 y(DUT)26 b(c)n(hip.)36 b(It)25 b(is)g(something)g(lik)n(e)f (\020DIP28\021)31 b(or)25 b(\020DIP40\021,)f(etc...)37 -b(.)f(If)25 b(this)h(param-)722 4872 y(eter)i(is)f(passed)g(to)g(the)h +b(.)f(If)25 b(this)h(param-)722 4972 y(eter)i(is)f(passed)g(to)g(the)h (constructor,)e(the)i(autogenerator)d(is)i(enabled.)1926 5255 y(6)p eop end %%Page: 7 7 diff --git a/libtoprammer/bit/.gitignore b/libtoprammer/bit/.gitignore deleted file mode 100644 index f9930d5..0000000 --- a/libtoprammer/bit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.build.log diff --git a/libtoprammer/bit/at27c256r.bit b/libtoprammer/bit/at27c256r.bit deleted file mode 100644 index 32a8c88..0000000 Binary files a/libtoprammer/bit/at27c256r.bit and /dev/null differ diff --git a/libtoprammer/bit/at89c2051dip20.bit b/libtoprammer/bit/at89c2051dip20.bit deleted file mode 100644 index e7d0b7e..0000000 Binary files a/libtoprammer/bit/at89c2051dip20.bit and /dev/null differ diff --git a/libtoprammer/bit/atmega32dip40.bit b/libtoprammer/bit/atmega32dip40.bit deleted file mode 100644 index 8a9ff73..0000000 Binary files a/libtoprammer/bit/atmega32dip40.bit and /dev/null differ diff --git a/libtoprammer/bit/atmega8dip28.bit b/libtoprammer/bit/atmega8dip28.bit deleted file mode 100644 index 445f63c..0000000 Binary files a/libtoprammer/bit/atmega8dip28.bit and /dev/null differ diff --git a/libtoprammer/bit/attiny13dip8.bit b/libtoprammer/bit/attiny13dip8.bit deleted file mode 100644 index 9278a35..0000000 Binary files a/libtoprammer/bit/attiny13dip8.bit and /dev/null differ diff --git a/libtoprammer/bit/attiny26dip20.bit b/libtoprammer/bit/attiny26dip20.bit deleted file mode 100644 index 4b5780b..0000000 Binary files a/libtoprammer/bit/attiny26dip20.bit and /dev/null differ diff --git a/libtoprammer/bit/build.sh b/libtoprammer/bit/build.sh deleted file mode 100755 index 8149afc..0000000 --- a/libtoprammer/bit/build.sh +++ /dev/null @@ -1,118 +0,0 @@ -#!/bin/sh -# Rebuild FPGA bit files -# Copyright (c) 2010-2012 Michael Buesch -# Licensed under the GNU/GPL v2+ - -basedir="$(dirname "$0")" -[ "$(echo -n "$basedir" | cut -c1)" = "/" ] || basedir="$PWD/$basedir" - -srcdir="$basedir/src" -bindir="$basedir" - - -die() -{ - echo "$*" >&2 - exit 1 -} - -terminate() -{ - die "Interrupted." -} - -trap terminate TERM INT - -usage() -{ - echo "Usage: build.sh [OPTIONS] [TARGETS]" - echo - echo "Options:" - echo " -h|--help Show this help text" - echo " -v|--verbose Verbose build" - echo - echo "Targets:" - echo "Specify the names of the targets to build, or leave blank to rebuild all." -} - -# Parse commandline -verbose=0 -targets="/" -while [ $# -gt 0 ]; do - [ "$1" = "-h" -o "$1" = "--help" ] && { - usage - exit 0 - } - [ "$1" = "-v" -o "$1" = "--verbose" ] && { - verbose=1 - shift - continue - } - target="$1" - target="${target%.bit}" # strip .bit suffix - # Add to list - targets="${targets}${target}/" - shift -done -[ "$targets" = "/" ] && targets= - -bitparser() -{ - python "$basedir/../bitfile.py" "$@" ||\ - die "Failed to execute bitparser" -} - -should_build() # $1=target -{ - target="$1" - [ "$target" = "template" ] && return 1 - [ -z "$targets" ] && return 0 - echo "$targets" | grep -qe '/'"$target"'/' -} - -# Check if the payload of two bitfiles matches -bitfile_is_equal() # $1=file1, $2=file2 -{ - [ -r $1 -a -r $2 ] || return 1 - bitparser "$1" NOACTION # Test if bitparser works - sum1="$(bitparser "$1" GETPAYLOAD | sha1sum -b - | awk '{print $1;}')" - sum2="$(bitparser "$2" GETPAYLOAD | sha1sum -b - | awk '{print $1;}')" - [ "$sum1" = "$sum2" ] -} - -for src in $srcdir/*; do - [ -d "$src" ] || continue - - srcname="$(basename $src)" - logfile="$bindir/$srcname.build.log" - - should_build $srcname || continue - - echo "Building $srcname..." - make -C $src/ clean >/dev/null ||\ - die "FAILED to clean $srcname." - if [ $verbose -eq 0 ]; then - make -C $src/ all >$logfile || { - cat $logfile - die "FAILED to build $srcname." - } - cat $logfile | grep WARNING - else - make -C $src/ all ||\ - die "FAILED to build $srcname." - fi - - new="$src/$srcname.bit" - old="$bindir/$srcname.bit" - if bitfile_is_equal "$old" "$new"; then - echo "Bitfile for target $srcname did not change" - else - cp -f "$new" "$old" - fi - make -C $src/ clean >/dev/null ||\ - die "FAILED to clean $srcname." - rm -f $logfile -done -echo "Successfully built all images." - -exit 0 diff --git a/libtoprammer/bit/hm62256dip28.bit b/libtoprammer/bit/hm62256dip28.bit deleted file mode 100644 index 9a74c4f..0000000 Binary files a/libtoprammer/bit/hm62256dip28.bit and /dev/null differ diff --git a/libtoprammer/bit/m24c16dip8.bit b/libtoprammer/bit/m24c16dip8.bit deleted file mode 100644 index e30149c..0000000 Binary files a/libtoprammer/bit/m24c16dip8.bit and /dev/null differ diff --git a/libtoprammer/bit/m2764a.bit b/libtoprammer/bit/m2764a.bit deleted file mode 100644 index cf1f8b5..0000000 Binary files a/libtoprammer/bit/m2764a.bit and /dev/null differ diff --git a/libtoprammer/bit/m8c-issp.bit b/libtoprammer/bit/m8c-issp.bit deleted file mode 100644 index c4c95c3..0000000 Binary files a/libtoprammer/bit/m8c-issp.bit and /dev/null differ diff --git a/libtoprammer/bit/src/.gitignore b/libtoprammer/bit/src/.gitignore deleted file mode 100644 index d0b5749..0000000 --- a/libtoprammer/bit/src/.gitignore +++ /dev/null @@ -1,29 +0,0 @@ -__xst/ -__ngo/ - -*.bgn -*.bit -*.bld -*.drc -*_map.map -*_map.mrp -*_map.ncd -*_map.ngm -*.ncd -*.ngc -*.ngd -*.ngr -*.pad -*_pad.csv -*_pad.txt -*.par -*.pcf -*.srp -*.unroutes -*_usage.xml -*_summary.xml -*.xpi -*.twr -*.ptwx -*.xrpt -xlnx_auto_* diff --git a/libtoprammer/bit/src/at27c256r/Makefile b/libtoprammer/bit/src/at27c256r/Makefile deleted file mode 100644 index 8c711ed..0000000 --- a/libtoprammer/bit/src/at27c256r/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=at27c256r -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.lso b/libtoprammer/bit/src/at27c256r/at27c256r.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.prj b/libtoprammer/bit/src/at27c256r/at27c256r.prj deleted file mode 100644 index 2dbbf55..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "at27c256r.v" diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.ucf b/libtoprammer/bit/src/at27c256r/at27c256r.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.ut b/libtoprammer/bit/src/at27c256r/at27c256r.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.v b/libtoprammer/bit/src/at27c256r/at27c256r.v deleted file mode 100644 index c14b4e5..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.v +++ /dev/null @@ -1,206 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel AT27C256R EPROM - * FPGA bottomhalf implementation - * - * Copyright (c) 2012 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h000C -`define RUNTIME_REV 16'h01 - -module at27c256r(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* Interface to the chip */ - reg [7:0] chip_data; - reg chip_data_en; - reg [14:0] chip_addr; - reg chip_ce; /* !CE */ - reg chip_prog_ce; /* !CE prog pulse */ - reg chip_prog_en; - wire chip_ce_wire; - reg chip_oe; /* !OE */ - - assign chip_ce_wire = chip_prog_en ? chip_prog_ce : chip_ce; - - reg [1:0] prog_busy; /* busy flag */ - reg [3:0] prog_state; /* prog state */ - - wire low, high; /* Constant lo/hi */ - assign low = 0; - assign high = 1; - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - initial begin - address <= 0; - read_data <= 0; - delay_count <= 0; - chip_data <= 0; - chip_data_en <= 0; - chip_addr <= 0; - chip_ce <= 1; - chip_prog_ce <= 1; - chip_prog_en <= 0; - chip_oe <= 1; - prog_busy <= 0; - prog_state <= 0; - end - - `define SET_BUSY prog_busy[0] <= !prog_busy[1] - `define IS_BUSY prog_busy[0] != prog_busy[1] - `define FINISH prog_busy[1] <= prog_busy[0] - - `define DELAY_100US delay_count <= 2400 - 1 /* 100uS */ - - always @(posedge osc) begin - if (delay_count == 0) begin - if (`IS_BUSY) begin - case (prog_state) - 0: begin - chip_prog_ce <= 0; - prog_state <= 1; - `DELAY_100US; - end - 1: begin - chip_prog_ce <= 1; - prog_state <= 0; - `FINISH; - end - endcase - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin /* Address low write */ - chip_addr[7:0] <= data[7:0]; - end - 8'h11: begin /* Address high write */ - chip_addr[14:8] <= data[6:0]; - end - 8'h12: begin /* Data pins write */ - chip_data[7:0] <= data[7:0]; - end - 8'h13: begin /* Flags write */ - chip_data_en <= data[0]; - chip_prog_en <= data[1]; - chip_ce <= data[2]; - chip_oe <= data[3]; - end - 8'h14: begin /* Perform prog pulse */ - `SET_BUSY; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Data pins read */ - read_data[2:0] <= zif[23:21]; - read_data[7:3] <= zif[29:25]; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, high); /* VPP */ - bufif0(zif[12], chip_addr[12], low); /* A12 */ - bufif0(zif[13], chip_addr[7], low); /* A7 */ - bufif0(zif[14], chip_addr[6], low); /* A6 */ - bufif0(zif[15], chip_addr[5], low); /* A5 */ - bufif0(zif[16], chip_addr[4], low); /* A4 */ - bufif0(zif[17], chip_addr[3], low); /* A3 */ - bufif0(zif[18], chip_addr[2], low); /* A2 */ - bufif0(zif[19], chip_addr[1], low); /* A1 */ - bufif0(zif[20], chip_addr[0], low); /* A0 */ - bufif0(zif[21], chip_data[0], !chip_data_en); /* O0 */ - bufif0(zif[22], chip_data[1], !chip_data_en); /* O1 */ - bufif0(zif[23], chip_data[2], !chip_data_en); /* O2 */ - bufif0(zif[24], low, low); /* GND */ - bufif0(zif[25], chip_data[3], !chip_data_en); /* O3 */ - bufif0(zif[26], chip_data[4], !chip_data_en); /* O4 */ - bufif0(zif[27], chip_data[5], !chip_data_en); /* O5 */ - bufif0(zif[28], chip_data[6], !chip_data_en); /* O6 */ - bufif0(zif[29], chip_data[7], !chip_data_en); /* O7 */ - bufif0(zif[30], chip_ce_wire, low); /* !CE */ - bufif0(zif[31], chip_addr[10], low); /* A10 */ - bufif0(zif[32], chip_oe, low); /* !OE */ - bufif0(zif[33], chip_addr[11], low); /* A11 */ - bufif0(zif[34], chip_addr[9], low); /* A9 */ - bufif0(zif[35], chip_addr[8], low); /* A8 */ - bufif0(zif[36], chip_addr[13], low); /* A13 */ - bufif0(zif[37], chip_addr[14], low); /* A14 */ - bufif0(zif[38], high, low); /* VCC */ - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/at27c256r/at27c256r.xst b/libtoprammer/bit/src/at27c256r/at27c256r.xst deleted file mode 100644 index 8a9df2b..0000000 --- a/libtoprammer/bit/src/at27c256r/at27c256r.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn at27c256r.prj --ifmt mixed --ofn at27c256r --ofmt NGC --p xc2s15-5-vq100 --top at27c256r --opt_mode Speed --opt_level 1 --iuc NO --lso at27c256r.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/at89c2051dip20/Makefile b/libtoprammer/bit/src/at89c2051dip20/Makefile deleted file mode 100644 index 7892761..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=at89c2051dip20 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.lso b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.prj b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.prj deleted file mode 100644 index d1309fc..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "at89c2051dip20.v" diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ucf b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ut b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.v b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.v deleted file mode 100644 index bc6dddb..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.v +++ /dev/null @@ -1,274 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel AT89C2051 DIP20 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Guido - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0005 -`define RUNTIME_REV 16'h01 - -module at89c2051dip20(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - /* Programmer context */ - reg [1:0] prog_busy; - reg [3:0] prog_command; - reg [3:0] prog_state; - reg [3:0] prog_count; - reg prog_err; - - /* DUT signals */ - reg [7:0] dut_data; - reg dut_p33; - reg dut_p34; - reg dut_p35; - reg dut_p37; - reg dut_ia; /* Increment Address */ - reg dut_prog; - reg dut_vpp; - - - assign low = 0; - assign high = 1; - - initial begin - prog_busy <= 0; - prog_command <= 0; - prog_state <= 0; - prog_err <= 0; - prog_count <= 0; - dut_data <= 0; - dut_p33 <= 0; - dut_p34 <= 0; - dut_p35 <= 0; - dut_p37 <= 0; - dut_ia <= 0; - dut_prog <= 0; - dut_vpp <= 0; - end - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - always @(posedge osc) begin - if (delay_count == 0) begin - if (prog_busy[0] != prog_busy[1]) begin - /* busy0 != busy1 indicates that a command is running. - * Continue executing it... */ - case (prog_command) - 1: begin /* Set P3.2 after init */ - dut_prog <= 1; - prog_busy[1] <= prog_busy[0]; - end - 2: begin /* clear P3.2 before shutdown */ - dut_prog <= 0; - prog_busy[1] <= prog_busy[0]; - end - 3: begin /* programm byte */ - case (prog_state) - 0: begin /* pulse */ - delay_count <= 24; - dut_prog <= 0; - prog_state <= 1; - prog_err <= 0; - end - 1: begin /* raise dut_prog */ - dut_prog <= 1; - prog_state <= 2; - prog_count <= 12; - delay_count <= 2; - end - 2: begin /* wait for ready == 1 */ - if (zif[17] == 0) begin - delay_count <= 4800; /* each 200 us */ - prog_count <= prog_count - 1; - if (prog_count == 0) begin - prog_err <= 1; - prog_state <= 3; - end - end - else begin - prog_state <= 3; - delay_count <= 24; - end - end - 3: begin /* finish */ - prog_state <= 0; - prog_busy[1] <= prog_busy[0]; - end - endcase - end - 4: begin /* chip erase */ - case (prog_state) - 0: begin /* start erasing */ - delay_count <= 24000; /* 1 ms each */ - prog_count <= 10; - dut_prog <= 0; - prog_state <= 1; - prog_err <= 0; - end - 1: begin /* loop */ - prog_count <= prog_count - 1; - if (prog_count == 0) begin - dut_prog <= 1; - prog_state <= 0; - prog_busy[1] <= prog_busy[0]; - end - else begin - delay_count <= 24000; - end - end - endcase - end - 5: begin /* set dut_vpp */ - dut_vpp <= 1; - prog_busy[1] <= prog_busy[0]; - end - 6: begin /* clear dut_vpp */ - dut_vpp <= 0; - prog_busy[1] <= prog_busy[0]; - end - endcase - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h12: begin - /* Run a command. */ - prog_command <= data; - prog_busy[0] <= ~prog_busy[1]; - end - 8'h16: begin - /* Set P33, P34, P35; IA */ - dut_p33 <= data[0]; - dut_p34 <= data[1]; - dut_p35 <= data[2]; - dut_p37 <= data[2]; - dut_ia <= data[3]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[7:0] <= zif[33:26]; - end - 8'h12: begin - /* Read status */ - read_data[0] <= (prog_busy[0] != prog_busy[1]); - read_data[1] <= prog_err; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, dut_vpp); /* VPP/Reset */ - bufif0(zif[16], low, low); /* P3.0 */ - bufif0(zif[17], low, high); /* P3.1 */ - bufif0(zif[18], low, low); /* XTAL2 */ - bufif0(zif[19], dut_ia, low); /* XTAL1 */ - bufif0(zif[20], dut_prog, low); /* P3.2 */ - bufif0(zif[21], dut_p33, low); /* P3.3 */ - bufif0(zif[22], dut_p34, low); /* P3.4 */ - bufif0(zif[23], dut_p35, low); /* P3.5 */ - bufif0(zif[24], low, low); /* GND */ - bufif0(zif[25], dut_p37, low); /* P3.7 */ - bufif0(zif[26], dut_data[0], !dut_p34); /* P1.0 */ - bufif0(zif[27], dut_data[1], !dut_p34); /* P1.1 */ - bufif0(zif[28], dut_data[2], !dut_p34); /* P1.2 */ - bufif0(zif[29], dut_data[3], !dut_p34); /* P1.3 */ - bufif0(zif[30], dut_data[4], !dut_p34); /* P1.4 */ - bufif0(zif[31], dut_data[5], !dut_p34); /* P1.5 */ - bufif0(zif[32], dut_data[6], !dut_p34); /* P1.6 */ - bufif0(zif[33], dut_data[7], !dut_p34); /* P1.7 */ - bufif0(zif[34], high, low); /* VCC */ - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.xst b/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.xst deleted file mode 100644 index a74a8f6..0000000 --- a/libtoprammer/bit/src/at89c2051dip20/at89c2051dip20.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn at89c2051dip20.prj --ifmt mixed --ofn at89c2051dip20 --ofmt NGC --p xc2s15-5-vq100 --top at89c2051dip20 --opt_mode Speed --opt_level 1 --iuc NO --lso at89c2051dip20.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/atmega32dip40/Makefile b/libtoprammer/bit/src/atmega32dip40/Makefile deleted file mode 100644 index f9e5acf..0000000 --- a/libtoprammer/bit/src/atmega32dip40/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=atmega32dip40 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj deleted file mode 100644 index 7f9b373..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "atmega32dip40.v" diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v deleted file mode 100644 index c95f857..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v +++ /dev/null @@ -1,203 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Mega32 DIP40 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010-2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0004 -`define RUNTIME_REV 16'h01 - -module atmega32dip40(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - reg [7:0] address; - reg [7:0] read_data; - wire read_oe; - - /* Signals to/from the DUT */ - reg dut_oe, dut_wr, dut_xtal, dut_pagel; - reg dut_bs1, dut_bs2; - reg dut_xa0, dut_xa1; - reg [7:0] dut_data; - reg dut_vpp_en; - reg dut_vpp; - reg dut_vcc_en; - reg dut_vcc; - - /* Constant lo/hi */ - wire low, high; - assign low = 0; - assign high = 1; - - initial begin - address <= 0; - read_data <= 0; - dut_oe <= 0; - dut_wr <= 0; - dut_xtal <= 0; - dut_pagel <= 0; - dut_bs1 <= 0; - dut_bs2 <= 0; - dut_xa0 <= 0; - dut_xa1 <= 0; - dut_data <= 0; - dut_vpp_en <= 0; - dut_vpp <= 0; - dut_vcc_en <= 0; - dut_vcc <= 0; - end - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin /* VCC/VPP control */ - dut_vpp_en <= data[0]; - dut_vpp <= data[1]; - dut_vcc_en <= data[2]; - dut_vcc <= data[3]; - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4: begin - dut_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6: begin - dut_xa1 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - 9: begin - dut_pagel <= data[7]; - end - 10: begin - dut_bs2 <= data[7]; - end - endcase - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data <= zif[32:25]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[39]; /* RDY */ - read_data[7:1] <= 0; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], dut_pagel, low); /* PD7, PAGEL */ - bufif0(zif[6], low, high); /* PC0 */ - bufif0(zif[7], low, high); /* PC1 */ - bufif0(zif[8], low, high); /* PC2 */ - bufif0(zif[9], low, high); /* PC3 */ - bufif0(zif[10], low, high); /* PC4 */ - bufif0(zif[11], low, high); /* PC5 */ - bufif0(zif[12], low, high); /* PC6 */ - bufif0(zif[13], low, high); /* PC7 */ - bufif0(zif[14], dut_vcc, !dut_vcc_en); /* AVCC */ - bufif0(zif[15], low, low); /* GND */ - bufif0(zif[16], low, high); /* AREF */ - bufif0(zif[17], low, high); /* PA7 */ - bufif0(zif[18], low, high); /* PA6 */ - bufif0(zif[19], low, high); /* PA5 */ - bufif0(zif[20], low, high); /* PA4 */ - bufif0(zif[21], low, high); /* PA3 */ - bufif0(zif[22], low, high); /* PA2 */ - bufif0(zif[23], low, high); /* PA1 */ - bufif0(zif[24], dut_bs2, low); /* PA0, BS2 */ - bufif0(zif[25], dut_data[0], !dut_oe); /* PB0, DATA0 */ - bufif0(zif[26], dut_data[1], !dut_oe); /* PB1, DATA1 */ - bufif0(zif[27], dut_data[2], !dut_oe); /* PB2, DATA2 */ - bufif0(zif[28], dut_data[3], !dut_oe); /* PB3, DATA3 */ - bufif0(zif[29], dut_data[4], !dut_oe); /* PB4, DATA4 */ - bufif0(zif[30], dut_data[5], !dut_oe); /* PB5, DATA5 */ - bufif0(zif[31], dut_data[6], !dut_oe); /* PB6, DATA6 */ - bufif0(zif[32], dut_data[7], !dut_oe); /* PB7, DATA7 */ - bufif0(zif[33], dut_vpp, !dut_vpp_en); /* /RESET */ - bufif0(zif[34], dut_vcc, !dut_vcc_en); /* VCC */ - bufif0(zif[35], low, low); /* GND */ - bufif0(zif[36], low, high); /* XTAL2 */ - bufif0(zif[37], dut_xtal, low); /* XTAL1 */ - bufif0(zif[38], low, high); /* PD0 */ - bufif0(zif[39], low, high); /* PD1, RDY/BSY */ - bufif0(zif[40], dut_oe, low); /* PD2, /OE */ - bufif0(zif[41], dut_wr, low); /* PD3, /WR */ - bufif0(zif[42], dut_bs1, low); /* PD4, BS1 */ - bufif0(zif[43], dut_xa0, low); /* PD5, XA0 */ - bufif0(zif[44], dut_xa1, low); /* PD6, XA1 */ - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst deleted file mode 100644 index fe2a54d..0000000 --- a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn atmega32dip40.prj --ifmt mixed --ofn atmega32dip40 --ofmt NGC --p xc2s15-5-vq100 --top atmega32dip40 --opt_mode Speed --opt_level 1 --iuc NO --lso atmega32dip40.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/atmega8dip28/Makefile b/libtoprammer/bit/src/atmega8dip28/Makefile deleted file mode 100644 index e9c0e99..0000000 --- a/libtoprammer/bit/src/atmega8dip28/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=atmega8dip28 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj deleted file mode 100644 index 25c6746..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "atmega8dip28.v" diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf deleted file mode 100644 index 7089175..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -#NET "osc" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; \ No newline at end of file diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v deleted file mode 100644 index b36f6fb..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v +++ /dev/null @@ -1,205 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Mega8 DIP28 - * Atmel Mega88 DIP28 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010-2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0003 -`define RUNTIME_REV 16'h01 - -module atmega8dip28(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - reg [7:0] address; - reg [7:0] read_data; - wire read_oe; - - /* Signals to/from the DUT */ - reg dut_oe, dut_wr, dut_xtal, dut_pagel; - reg dut_bs1, dut_bs2; - reg dut_xa0, dut_xa1; - reg [7:0] dut_data; - reg dut_vpp_en; - reg dut_vpp; - reg dut_vcc_en; - reg dut_vcc; - - /* Constant lo/hi */ - wire low, high; - assign low = 0; - assign high = 1; - - initial begin - address <= 0; - read_data <= 0; - dut_oe <= 0; - dut_wr <= 0; - dut_xtal <= 0; - dut_pagel <= 0; - dut_bs1 <= 0; - dut_bs2 <= 0; - dut_xa0 <= 0; - dut_xa1 <= 0; - dut_data <= 0; - dut_vpp_en <= 0; - dut_vpp <= 0; - dut_vcc_en <= 0; - dut_vcc <= 0; - end - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin /* VCC/VPP control */ - dut_vpp_en <= data[0]; - dut_vpp <= data[1]; - dut_vcc_en <= data[2]; - dut_vcc <= data[3]; - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4: begin - dut_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6: begin - dut_xa1 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - 9: begin - dut_pagel <= data[7]; - end - 10: begin - dut_bs2 <= data[7]; - end - endcase - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[5:0] <= zif[29:24]; - read_data[7:6] <= zif[34:33]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[13]; /* RDY */ - read_data[7:1] <= 0; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], dut_vpp, !dut_vpp_en); /* PC6, /RESET */ - bufif0(zif[12], low, high); /* PD0 */ - bufif0(zif[13], low, high); /* PD1, RDY/BSY */ - bufif0(zif[14], dut_oe, low); /* PD2, /OE */ - bufif0(zif[15], dut_wr, low); /* PD3, /WR */ - bufif0(zif[16], dut_bs1, low); /* PD4, BS1 */ - bufif0(zif[17], dut_vcc, !dut_vcc_en); /* VCC */ - bufif0(zif[18], low, low); /* GND */ - bufif0(zif[19], dut_xtal, low); /* PB6, XTAL1 */ - bufif0(zif[20], low, high); /* PB7, XTAL2 */ - bufif0(zif[21], dut_xa0, low); /* PD5, XA0 */ - bufif0(zif[22], dut_xa1, low); /* PD6, XA1 */ - bufif0(zif[23], dut_pagel, low); /* PD7, PAGEL */ - bufif0(zif[24], dut_data[0], !dut_oe); /* PB0, DATA0 */ - bufif0(zif[25], dut_data[1], !dut_oe); /* PB1, DATA1 */ - bufif0(zif[26], dut_data[2], !dut_oe); /* PB2, DATA2 */ - bufif0(zif[27], dut_data[3], !dut_oe); /* PB3, DATA3 */ - bufif0(zif[28], dut_data[4], !dut_oe); /* PB4, DATA4 */ - bufif0(zif[29], dut_data[5], !dut_oe); /* PB5, DATA5 */ - bufif0(zif[30], dut_vcc, !dut_vcc_en); /* AVCC */ - bufif0(zif[31], low, high); /* AREF */ - bufif0(zif[32], low, low); /* GND */ - bufif0(zif[33], dut_data[6], !dut_oe); /* PC0, DATA6 */ - bufif0(zif[34], dut_data[7], !dut_oe); /* PC1, DATA7 */ - bufif0(zif[35], dut_bs2, low); /* PC2, BS2 */ - bufif0(zif[36], low, high); /* PC3 */ - bufif0(zif[37], low, high); /* PC4 */ - bufif0(zif[38], low, high); /* PC5 */ - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst deleted file mode 100644 index dd040ec..0000000 --- a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn atmega8dip28.prj --ifmt mixed --ofn atmega8dip28 --ofmt NGC --p xc2s15-5-vq100 --top atmega8dip28 --opt_mode Speed --opt_level 1 --iuc NO --lso atmega8dip28.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/attiny13dip8/Makefile b/libtoprammer/bit/src/attiny13dip8/Makefile deleted file mode 100644 index c561e61..0000000 --- a/libtoprammer/bit/src/attiny13dip8/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=attiny13dip8 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.lso b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.prj b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.prj deleted file mode 100644 index a77d390..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "attiny13dip8.v" diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ucf b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ut b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.v b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.v deleted file mode 100644 index 44d9822..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.v +++ /dev/null @@ -1,244 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Tiny13 DIP8 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0001 -`define RUNTIME_REV 16'h01 - -module attiny13dip8(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* Programmer context */ - reg [1:0] prog_busy; - reg [7:0] prog_command; - reg [7:0] prog_state; - reg [7:0] prog_count; - `define CMD_SENDINSTR 1 - reg dut_sdi; - reg dut_sii; - reg dut_sci_manual; - reg dut_sci_auto; - wire dut_sci; - reg dut_sdo_driven; - reg dut_sdo_value; - reg dut_rst_driven; - reg dut_rst_value; - `define DUT_SDO 33 - reg [10:0] sdi_buf; - reg [10:0] sii_buf; - reg [10:0] sdo_buf; - - wire low, high; /* Constant lo/hi */ - assign low = 0; - assign high = 1; - - initial begin - prog_busy <= 0; - prog_command <= 0; - prog_state <= 0; - prog_count <= 0; - dut_sdi <= 0; - dut_sii <= 0; - dut_sci_manual <= 0; - dut_sci_auto <= 0; - dut_sdo_driven <= 0; - dut_sdo_value <= 0; - dut_rst_driven <= 0; - dut_rst_value <= 0; - sdi_buf <= 0; - sii_buf <= 0; - sdo_buf <= 0; - end - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - `define DELAY_1US delay_count <= 24 - 1 - - always @(posedge osc) begin - if (delay_count == 0 && prog_busy[0] != prog_busy[1]) begin - case (prog_command) - `CMD_SENDINSTR: begin - case (prog_state) - 0: begin - dut_sdi <= sdi_buf[10 - prog_count]; - dut_sii <= sii_buf[10 - prog_count]; - prog_state <= 1; - `DELAY_1US; - end - 1: begin - dut_sci_auto <= 1; /* CLK hi */ - prog_state <= 2; - `DELAY_1US; - end - 2: begin - sdo_buf[10 - prog_count] <= zif[`DUT_SDO]; - prog_count <= prog_count + 1; - prog_state <= 3; - `DELAY_1US; - end - 3: begin - dut_sci_auto <= 0; /* CLK lo */ - `DELAY_1US; - if (prog_count == 11) begin - prog_state <= 0; - prog_count <= 0; - prog_busy[1] <= prog_busy[0]; /* done */ - end else begin - prog_state <= 0; - end - end - endcase - end - endcase - end else begin - if (delay_count != 0) begin - delay_count <= delay_count - 1; - end - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin /* Unused */ - end - 8'h12: begin /* Run command */ - prog_command <= data; - prog_busy[0] <= ~prog_busy[1]; - end - 8'h13: begin /* Load SDI sequence */ - sdi_buf[1:0] <= 0; - sdi_buf[9:2] <= data; - sdi_buf[10] <= 0; - end - 8'h14: begin /* Load SII sequence */ - sii_buf[1:0] <= 0; - sii_buf[9:2] <= data; - sii_buf[10] <= 0; - end - 8'h15: begin /* Set signals manually */ - dut_sci_manual <= data[0]; /* SCI */ - dut_sdo_driven <= data[1]; /* SDO drive-enable */ - dut_sdo_value <= data[2]; /* SDO drive-value */ - dut_rst_driven <= data[3]; /* RESET drive-enable */ - dut_rst_value <= data[4]; /* RESET drive-value */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Get SDO sequence high (bits 3-10) */ - read_data[7:0] <= sdo_buf[10:3]; - end - 8'h12: begin /* Read status */ - read_data[0] <= (prog_busy[0] != prog_busy[1]); /* busy */ - read_data[1] <= zif[`DUT_SDO]; /* Raw SDO pin access */ - end - 8'h13: begin /* Get SDO sequence low (bits 0-7) */ - read_data[7:0] <= sdo_buf[7:0]; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign dut_sci = (prog_busy[0] == prog_busy[1]) ? dut_sci_manual : dut_sci_auto; - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], dut_rst_value, !dut_rst_driven); /* RESET */ - bufif0(zif[16], dut_sci, low); /* SCI */ - bufif0(zif[17], low, high); /* PB4 */ - bufif0(zif[18], low, low); /* GND */ - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); - bufif0(zif[21], low, low); - bufif0(zif[22], low, low); - bufif0(zif[23], low, low); - bufif0(zif[24], low, low); - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], low, low); - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], dut_sdi, low); /* SDI */ - bufif0(zif[32], dut_sii, low); /* SII */ - bufif0(zif[33], dut_sdo_value, !dut_sdo_driven); /* SDO */ - bufif0(zif[34], high, low); /* VCC */ - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.xst b/libtoprammer/bit/src/attiny13dip8/attiny13dip8.xst deleted file mode 100644 index 84d1e50..0000000 --- a/libtoprammer/bit/src/attiny13dip8/attiny13dip8.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn attiny13dip8.prj --ifmt mixed --ofn attiny13dip8 --ofmt NGC --p xc2s15-5-vq100 --top attiny13dip8 --opt_mode Speed --opt_level 1 --iuc NO --lso attiny13dip8.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/attiny26dip20/Makefile b/libtoprammer/bit/src/attiny26dip20/Makefile deleted file mode 100644 index 4471481..0000000 --- a/libtoprammer/bit/src/attiny26dip20/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=attiny26dip20 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.lso b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.prj b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.prj deleted file mode 100644 index 44ed439..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "attiny26dip20.v" diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ucf b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ut b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.v b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.v deleted file mode 100644 index b4c17aa..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.v +++ /dev/null @@ -1,201 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Tiny26 DIP20 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010-2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0002 -`define RUNTIME_REV 16'h01 - -module attiny26dip20(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - reg [7:0] address; - reg [7:0] read_data; - wire read_oe; - - /* Signals to/from the DUT */ - reg dut_oe, dut_wr, dut_xtal, dut_pagel_bs1; - reg dut_xa0, dut_xa1_bs2; - reg [7:0] dut_data; - reg dut_vpp_en; - reg dut_vpp; - reg dut_vcc_en; - reg dut_vcc; - - /* Constant lo/hi */ - wire low, high; - assign low = 0; - assign high = 1; - - initial begin - address <= 0; - read_data <= 0; - dut_oe <= 0; - dut_wr <= 0; - dut_xtal <= 0; - dut_pagel_bs1 <= 0; - dut_xa0 <= 0; - dut_xa1_bs2 <= 0; - dut_data <= 0; - dut_vpp_en <= 0; - dut_vpp <= 0; - dut_vcc_en <= 0; - dut_vcc <= 0; - end - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin /* VCC/VPP control */ - dut_vpp_en <= data[0]; - dut_vpp <= data[1]; - dut_vcc_en <= data[2]; - dut_vcc <= data[3]; - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4, 9: begin - dut_pagel_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6, 10: begin - dut_xa1_bs2 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - endcase - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[0] <= zif[21]; - read_data[1] <= zif[20]; - read_data[2] <= zif[19]; - read_data[3] <= zif[18]; - read_data[4] <= zif[15]; - read_data[5] <= zif[14]; - read_data[6] <= zif[13]; - read_data[7] <= zif[12]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[36]; /* RDY */ - read_data[7:1] <= 0; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], dut_data[7], !dut_oe); /* PA7, DATA7 */ - bufif0(zif[13], dut_data[6], !dut_oe); /* PA6, DATA6 */ - bufif0(zif[14], dut_data[5], !dut_oe); /* PA5, DATA5 */ - bufif0(zif[15], dut_data[4], !dut_oe); /* PA4, DATA4 */ - bufif0(zif[16], dut_vcc, !dut_vcc_en); /* AVCC */ - bufif0(zif[17], low, low); /* GND */ - bufif0(zif[18], dut_data[3], !dut_oe); /* PA3, DATA3 */ - bufif0(zif[19], dut_data[2], !dut_oe); /* PA2, DATA2 */ - bufif0(zif[20], dut_data[1], !dut_oe); /* PA1, DATA1 */ - bufif0(zif[21], dut_data[0], !dut_oe); /* PA0, DATA0 */ - bufif0(zif[22], low, low); - bufif0(zif[23], low, low); - bufif0(zif[24], low, low); - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], dut_wr, low); /* PB0, /WR */ - bufif0(zif[29], dut_xa0, low); /* PB1, XA0 */ - bufif0(zif[30], dut_xa1_bs2, low); /* PB2, XA1/BS2 */ - bufif0(zif[31], dut_pagel_bs1, low); /* PB3, PAGEL/BS1 */ - bufif0(zif[32], dut_vcc, !dut_vcc_en); /* VCC */ - bufif0(zif[33], low, low); /* GND */ - bufif0(zif[34], dut_xtal, low); /* PB4, XTAL1 */ - bufif0(zif[35], dut_oe, low); /* PB5, XTAL2, /OE */ - bufif0(zif[36], low, high); /* PB6, RDY/BSY */ - bufif0(zif[37], dut_vpp, !dut_vpp_en); /* PB7, /RESET */ - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.xst b/libtoprammer/bit/src/attiny26dip20/attiny26dip20.xst deleted file mode 100644 index 6ef06ea..0000000 --- a/libtoprammer/bit/src/attiny26dip20/attiny26dip20.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn attiny26dip20.prj --ifmt mixed --ofn attiny26dip20 --ofmt NGC --p xc2s15-5-vq100 --top attiny26dip20 --opt_mode Speed --opt_level 1 --iuc NO --lso attiny26dip20.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/create.sh b/libtoprammer/bit/src/create.sh deleted file mode 100755 index 7c8214c..0000000 --- a/libtoprammer/bit/src/create.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/bin/sh -# Create source template -# Copyright (c) 2010-2012 Michael Buesch -# Licensed under the GNU/GPL v2+ - -basedir="$(dirname "$0")" -[ "$(echo -n "$basedir" | cut -c1)" = "/" ] || basedir="$PWD/$basedir" - -template="$basedir/template" - -set -e - -usage() -{ - echo "Usage: create.sh TARGET_NAME" -} - -[ $# -eq 1 ] || { - usage - exit 1 -} -name="$1" - -target="$basedir/$name" - -mkdir -p "$target" -for file in $(ls "$template"); do - suffix="$(echo "$file" | cut -d. -f2)" - targetfile="$name.$suffix" - [ "$file" = "Makefile" ] && targetfile="$file" - cat "$template/$file" |\ - sed -e 's/template/'"$name"'/' > "$target/$targetfile" -done - -exit 0 diff --git a/libtoprammer/bit/src/hm62256dip28/Makefile b/libtoprammer/bit/src/hm62256dip28/Makefile deleted file mode 100644 index 93af85c..0000000 --- a/libtoprammer/bit/src/hm62256dip28/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=hm62256dip28 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.lso b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.prj b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.prj deleted file mode 100644 index a9e7dd8..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "hm62256dip28.v" diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ucf b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ucf deleted file mode 100644 index 8c2d654..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -//NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ut b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.v b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.v deleted file mode 100644 index 0cda827..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.v +++ /dev/null @@ -1,153 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * HM62256 SRAM - * FPGA bottomhalf implementation - * - * Copyright (c) 2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h000A -`define RUNTIME_REV 16'h01 - -module hm62256dip28(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* Chip (DUT) signals */ - reg [14:0] dut_addr; - reg [7:0] dut_data; - reg dut_ce; - reg dut_oe; - reg dut_we; - - wire low, high; /* Constant lo/hi */ - - assign low = 0; - assign high = 1; - - always @(posedge write) begin - case (address) - 8'h10: begin /* Bulk write */ - dut_data <= data; - end - 8'h11: begin /* /CE, /OE, /WE */ - dut_ce <= data[0]; - dut_oe <= data[1]; - dut_we <= data[2]; - end - 8'h12: begin /* Addr byte 0 */ - dut_addr[7:0] <= data[7:0]; - end - 8'h13: begin /* Addr byte 1 */ - dut_addr[14:8] <= data[6:0]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Bulk read */ - read_data[0] <= zif[21]; - read_data[1] <= zif[22]; - read_data[2] <= zif[23]; - read_data[3] <= zif[25]; - read_data[4] <= zif[26]; - read_data[5] <= zif[27]; - read_data[6] <= zif[28]; - read_data[7] <= zif[29]; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], dut_addr[14], low); /* A14 */ - bufif0(zif[12], dut_addr[12], low); /* A12 */ - bufif0(zif[13], dut_addr[7], low); /* A7 */ - bufif0(zif[14], dut_addr[6], low); /* A6 */ - bufif0(zif[15], dut_addr[5], low); /* A5 */ - bufif0(zif[16], dut_addr[4], low); /* A4 */ - bufif0(zif[17], dut_addr[3], low); /* A3 */ - bufif0(zif[18], dut_addr[2], low); /* A2 */ - bufif0(zif[19], dut_addr[1], low); /* A1 */ - bufif0(zif[20], dut_addr[0], low); /* A0 */ - bufif0(zif[21], dut_data[0], !dut_oe); /* DQ0 */ - bufif0(zif[22], dut_data[1], !dut_oe); /* DQ1 */ - bufif0(zif[23], dut_data[2], !dut_oe); /* DQ2 */ - bufif0(zif[24], low, low); /* GND */ - bufif0(zif[25], dut_data[3], !dut_oe); /* DQ3 */ - bufif0(zif[26], dut_data[4], !dut_oe); /* DQ4 */ - bufif0(zif[27], dut_data[5], !dut_oe); /* DQ5 */ - bufif0(zif[28], dut_data[6], !dut_oe); /* DQ6 */ - bufif0(zif[29], dut_data[7], !dut_oe); /* DQ7 */ - bufif0(zif[30], dut_ce, low); /* /CE */ - bufif0(zif[31], dut_addr[10], low); /* A10 */ - bufif0(zif[32], dut_oe, low); /* /OE */ - bufif0(zif[33], dut_addr[11], low); /* A11 */ - bufif0(zif[34], dut_addr[9], low); /* A9 */ - bufif0(zif[35], dut_addr[8], low); /* A8 */ - bufif0(zif[36], dut_addr[13], low); /* A13 */ - bufif0(zif[37], dut_we, low); /* /WE */ - bufif0(zif[38], high, low); /* VCC */ - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.xst b/libtoprammer/bit/src/hm62256dip28/hm62256dip28.xst deleted file mode 100644 index 702578f..0000000 --- a/libtoprammer/bit/src/hm62256dip28/hm62256dip28.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn hm62256dip28.prj --ifmt mixed --ofn hm62256dip28 --ofmt NGC --p xc2s15-5-vq100 --top hm62256dip28 --opt_mode Speed --opt_level 1 --iuc NO --lso hm62256dip28.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/m24c16dip8/Makefile b/libtoprammer/bit/src/m24c16dip8/Makefile deleted file mode 100644 index 8cb5e97..0000000 --- a/libtoprammer/bit/src/m24c16dip8/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=m24c16dip8 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.lso b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.prj b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.prj deleted file mode 100644 index 6478642..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "m24c16dip8.v" diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ucf b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ucf deleted file mode 100644 index a550c07..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale_in" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ut b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.v b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.v deleted file mode 100644 index 8120b41..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.v +++ /dev/null @@ -1,512 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * M24C16 I2C based serial EEPROM - * FPGA bottomhalf implementation - * - * Copyright (c) 2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h000B -`define RUNTIME_REV 16'h01 - -module i2c_module(clock, scl, sda, - write_byte, read_byte, read_mode, - do_start, expect_ack, do_stop, - finished); - input clock; - output scl; - inout sda; - input [7:0] write_byte; - output [7:0] read_byte; - input read_mode; - input do_start; - input expect_ack; - input do_stop; - output finished; - - reg [7:0] start_state; - reg [7:0] data_state; - reg [7:0] ack_state; - reg [7:0] stop_state; - reg [2:0] bit_index; - - reg sda_out; - reg sda_out_en; - reg scl_out; - reg [7:0] read_byte_out; - reg finished_out; - - initial begin - start_state <= 0; - data_state <= 0; - ack_state <= 0; - stop_state <= 0; - bit_index <= 0; - - sda_out <= 0; - sda_out_en <= 0; - scl_out <= 0; - read_byte_out <= 0; - finished_out <= 0; - end - - always @(posedge clock) begin - if (do_start && start_state != 3) begin - /* Send start condition */ - finished_out <= 0; - sda_out_en <= 1; - case (start_state) - 0: begin - /* Start SCL high */ - scl_out <= 1; - sda_out <= 1; - start_state <= 1; - end - 1: begin - /* Start condition latch */ - sda_out <= 0; - start_state <= 2; - end - 2: begin - /* Start SCL low */ - scl_out <= 0; - start_state <= 3; - end - endcase - end else if (data_state != 3) begin - /* Data transfer */ - finished_out <= 0; - if (read_mode) begin /* Read */ - sda_out_en <= 0; - sda_out <= 0; - case (data_state) - 0: begin - scl_out <= 1; - data_state <= 1; - end - 1: begin - read_byte_out[7 - bit_index] <= sda; - data_state <= 2; - end - 2: begin - scl_out <= 0; - if (bit_index == 7) begin - /* Done reading byte */ - bit_index <= 0; - data_state <= 3; - end else begin - bit_index <= bit_index + 1; - data_state <= 0; - end - end - endcase - end else begin /* Write */ - sda_out_en <= 1; - case (data_state) - 0: begin - sda_out <= write_byte[7 - bit_index]; - scl_out <= 0; - data_state <= 1; - end - 1: begin - scl_out <= 1; - data_state <= 2; - end - 2: begin - scl_out <= 0; - if (bit_index == 7) begin - /* Done writing byte */ - bit_index <= 0; - data_state <= 3; - end else begin - bit_index <= bit_index + 1; - data_state <= 0; - end - end - endcase - end - end else if (expect_ack && ack_state != 2) begin - /* Wait for ACK from chip */ - finished_out <= 0; - sda_out_en <= 0; - case (ack_state) - 0: begin - scl_out <= 1; - ack_state <= 1; - end - 1: begin - scl_out <= 0; - if (sda == 0) begin - /* Got it */ - ack_state <= 2; - end else begin - ack_state <= 0; - end - end - endcase - end else if (do_stop && stop_state != 3) begin - /* Send stop condition */ - finished_out <= 0; - sda_out_en <= 1; - case (stop_state) - 0: begin - scl_out <= 1; - sda_out <= 0; - stop_state <= 1; - end - 1: begin - sda_out <= 1; - stop_state <= 2; - end - 2: begin - stop_state <= 3; - end - endcase - end else begin - /* Reset */ - start_state <= 0; - data_state <= 0; - ack_state <= 0; - stop_state <= 0; - - finished_out <= 1; - end - end - - bufif1(sda, sda_out, sda_out_en); - bufif1(scl, scl_out, 1); - bufif1(read_byte[0], read_byte_out[0], 1); - bufif1(read_byte[1], read_byte_out[1], 1); - bufif1(read_byte[2], read_byte_out[2], 1); - bufif1(read_byte[3], read_byte_out[3], 1); - bufif1(read_byte[4], read_byte_out[4], 1); - bufif1(read_byte[5], read_byte_out[5], 1); - bufif1(read_byte[6], read_byte_out[6], 1); - bufif1(read_byte[7], read_byte_out[7], 1); - bufif1(finished, finished_out, 1); -endmodule - -module m24c16dip8(data, ale_in, write, read, osc_in, zif); - inout [7:0] data; - input ale_in; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* Programmer API and statemachine */ - reg [1:0] cmd_busy; /* bit0 != bit1 >= busy */ - reg [3:0] command; - reg [7:0] data_buffer; - reg [7:0] addr_buffer; - - `define IS_BUSY (cmd_busy[0] != cmd_busy[1]) /* Is running command? */ - `define SET_FINISHED cmd_busy[1] <= cmd_busy[0] /* Set command-finished */ - - /* Programmer commands */ - parameter CMD_DEVSEL_READ = 0; - parameter CMD_DEVSEL_WRITE = 1; - parameter CMD_SETADDR = 2; - parameter CMD_DATA_READ = 3; - parameter CMD_DATA_READ_STOP = 4; - parameter CMD_DATA_WRITE = 5; - parameter CMD_DATA_WRITE_STOP = 6; - - /* Chip signals */ - reg chip_e0; /* E0 */ - reg chip_e0_en; /* E0 enable */ - reg chip_e1; /* E1 */ - reg chip_e1_en; /* E1 enable */ - reg chip_e2; /* E2 */ - reg chip_e2_en; /* E2 enable */ - reg chip_wc; /* /WC */ - parameter ZIF_SDA = 25; - parameter ZIF_SCL = 26; - - wire low, high; /* Constant lo/hi */ - assign low = 0; - assign high = 1; - - /* I2C interface */ - reg i2c_clock; - reg [7:0] i2c_write_byte; - wire [7:0] i2c_read_byte; - reg i2c_read; /* 1=> Read mode */ - reg i2c_do_start; - reg i2c_expect_ack; - reg i2c_do_stop; - wire i2c_finished; - reg [1:0] i2c_running; - - i2c_module i2c(.clock(i2c_clock), .scl(zif[ZIF_SCL]), .sda(zif[ZIF_SDA]), - .write_byte(i2c_write_byte), .read_byte(i2c_read_byte), .read_mode(i2c_read), - .do_start(i2c_do_start), .expect_ack(i2c_expect_ack), .do_stop(i2c_do_stop), - .finished(i2c_finished)); - - /* Cached data from byte read operation */ - reg [7:0] fetched_data; - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - `define DELAY_1P5US delay_count <= 36 - 1 /* 1.5 microseconds */ - - initial begin - address <= 0; - read_data <= 0; - delay_count <= 0; - - cmd_busy <= 0; - command <= 0; - data_buffer <= 0; - addr_buffer <= 0; - - chip_e0 <= 0; - chip_e0_en <= 0; - chip_e1 <= 0; - chip_e1_en <= 0; - chip_e2 <= 0; - chip_e2_en <= 0; - chip_wc <= 0; - - i2c_clock <= 0; - i2c_write_byte <= 0; - i2c_read <= 0; - i2c_do_start <= 0; - i2c_expect_ack <= 0; - i2c_do_stop <= 0; - i2c_running <= 0; - - fetched_data <= 0; - end - - always @(posedge osc) begin - if (delay_count == 0 && `IS_BUSY) begin - if (i2c_running) begin - if (i2c_finished && i2c_running == 2) begin - i2c_running <= 0; - if (i2c_read) begin - fetched_data <= i2c_read_byte; - end - `SET_FINISHED; - end else begin - i2c_running <= 2; - i2c_clock <= ~i2c_clock; - `DELAY_1P5US; - end - end else begin - case (command) - CMD_DEVSEL_READ: begin - i2c_write_byte[7] <= 1; - i2c_write_byte[6] <= 0; - i2c_write_byte[5] <= 1; - i2c_write_byte[4] <= 0; - i2c_write_byte[3] <= chip_e2; - i2c_write_byte[2] <= chip_e1; - i2c_write_byte[1] <= chip_e0; - i2c_write_byte[0] <= 1; /* Read */ - i2c_clock <= 0; - i2c_read <= 0; - i2c_do_start <= 1; - i2c_expect_ack <= 1; - i2c_do_stop <= 0; - i2c_running <= 1; - end - CMD_DEVSEL_WRITE: begin - i2c_write_byte[7] <= 1; - i2c_write_byte[6] <= 0; - i2c_write_byte[5] <= 1; - i2c_write_byte[4] <= 0; - i2c_write_byte[3] <= chip_e2; - i2c_write_byte[2] <= chip_e1; - i2c_write_byte[1] <= chip_e0; - i2c_write_byte[0] <= 0; /* Write */ - i2c_clock <= 0; - i2c_read <= 0; - i2c_do_start <= 1; - i2c_expect_ack <= 1; - i2c_do_stop <= 0; - i2c_running <= 1; - end - CMD_SETADDR: begin - i2c_write_byte <= addr_buffer; - i2c_clock <= 0; - i2c_read <= 0; - i2c_do_start <= 0; - i2c_expect_ack <= 1; - i2c_do_stop <= 0; - i2c_running <= 1; - end - CMD_DATA_READ: begin - i2c_clock <= 0; - i2c_read <= 1; - i2c_do_start <= 0; - i2c_expect_ack <= 1; - i2c_do_stop <= 0; - i2c_running <= 1; - end - CMD_DATA_READ_STOP: begin - i2c_clock <= 0; - i2c_read <= 1; - i2c_do_start <= 0; - i2c_expect_ack <= 0; - i2c_do_stop <= 1; - i2c_running <= 1; - end - CMD_DATA_WRITE: begin - i2c_write_byte <= data_buffer; - i2c_clock <= 0; - i2c_read <= 0; - i2c_do_start <= 0; - i2c_expect_ack <= 1; - i2c_do_stop <= 0; - i2c_running <= 1; - end - CMD_DATA_WRITE_STOP: begin - i2c_write_byte <= data_buffer; - i2c_clock <= 0; - i2c_read <= 0; - i2c_do_start <= 0; - i2c_expect_ack <= 1; - i2c_do_stop <= 1; - i2c_running <= 1; - end - endcase - end - end else begin - if (delay_count != 0) begin - delay_count <= delay_count - 1; - end - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin /* Run command */ - command <= data; - cmd_busy[0] <= ~cmd_busy[1]; - end - 8'h11: begin /* Write to addr buffer */ - addr_buffer[7:0] <= data[7:0]; - end - 8'h12: begin /* Write to data buffer */ - data_buffer[7:0] <= data[7:0]; - end - 8'h13: begin /* Set control pins */ - chip_e0 <= data[0]; - chip_e0_en <= data[1]; - chip_e1 <= data[2]; - chip_e1_en <= data[3]; - chip_e2 <= data[4]; - chip_e2_en <= data[5]; - chip_wc <= data[6]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Read data buffer */ - read_data <= fetched_data; - end - 8'h11: begin /* Status read */ - read_data[0] <= cmd_busy[0]; - read_data[1] <= cmd_busy[1]; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - wire ale; - IBUFG ale_ibufg(.I(ale_in), .O(ale)); - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); - bufif0(zif[21], chip_e0, !chip_e0_en); /* E0 */ - bufif0(zif[22], chip_e1, !chip_e1_en); /* E1 */ - bufif0(zif[23], chip_e2, !chip_e2_en); /* E2 */ - bufif0(zif[24], low, low); /* VSS */ -/* bufif0(zif[25], low, high); */ /* SDA; driven by i2c module. */ -/* bufif0(zif[26], low, high); */ /* SCL; driven by i2c module. */ - bufif0(zif[27], chip_wc, low); /* /WC */ - bufif0(zif[28], high, low); /* VCC */ - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], low, low); - bufif0(zif[34], low, low); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.xst b/libtoprammer/bit/src/m24c16dip8/m24c16dip8.xst deleted file mode 100644 index 99287c5..0000000 --- a/libtoprammer/bit/src/m24c16dip8/m24c16dip8.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn m24c16dip8.prj --ifmt mixed --ofn m24c16dip8 --ofmt NGC --p xc2s15-5-vq100 --top m24c16dip8 --opt_mode Speed --opt_level 1 --iuc NO --lso m24c16dip8.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/m2764a/Makefile b/libtoprammer/bit/src/m2764a/Makefile deleted file mode 100644 index 6ce9d6e..0000000 --- a/libtoprammer/bit/src/m2764a/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=m2764a -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/m2764a/m2764a.lso b/libtoprammer/bit/src/m2764a/m2764a.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/m2764a/m2764a.prj b/libtoprammer/bit/src/m2764a/m2764a.prj deleted file mode 100644 index 25e4d2c..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "m2764a.v" diff --git a/libtoprammer/bit/src/m2764a/m2764a.ucf b/libtoprammer/bit/src/m2764a/m2764a.ucf deleted file mode 100644 index 17f86dc..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/m2764a/m2764a.ut b/libtoprammer/bit/src/m2764a/m2764a.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/m2764a/m2764a.v b/libtoprammer/bit/src/m2764a/m2764a.v deleted file mode 100644 index 184ca16..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.v +++ /dev/null @@ -1,230 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * M2764A EPROM - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0006 -`define RUNTIME_REV 16'h01 - -module m2764a(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - /* Programmer context */ - reg [1:0] prog_busy; - reg [3:0] prog_command; - reg [3:0] prog_state; - reg [7:0] prog_pulselen; - reg [7:0] prog_count; - `define PROG_PPULSE 1 - - /* DUT signals */ - reg [12:0] dut_addr; - reg [7:0] dut_data; - reg dut_E; - reg dut_P; - reg dut_G; - - assign low = 0; - assign high = 1; - - initial begin - prog_busy <= 0; - prog_command <= 0; - prog_state <= 0; - prog_pulselen <= 0; - prog_count <= 0; - dut_addr <= 0; - dut_data <= 0; - dut_E <= 1; - dut_P <= 1; - dut_G <= 1; - end - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - always @(posedge osc) begin - if (delay_count == 0) begin - if (prog_busy[0] != prog_busy[1]) begin - /* busy0 != busy1 indicates that a command is running. - * Continue executing it... */ - - case (prog_command) - `PROG_PPULSE: begin - case (prog_state) - 0: begin /* Init */ - dut_P <= 0; - prog_count <= prog_pulselen - 1; - prog_state <= 1; - delay_count <= 24000 - 2; - end - 1: begin /* Delay loop */ - if (prog_count == 0) begin - /* Done */ - dut_P <= 1; - prog_state <= 0; - prog_busy[1] <= prog_busy[0]; - end else begin - prog_state <= 2; - delay_count <= 24000 - 2; - end - end - 2: begin - prog_count <= prog_count - 1; - prog_state <= 1; - end - endcase - end - endcase - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h12: begin - /* Run a command. */ - prog_command <= data; - prog_busy[0] <= ~prog_busy[1]; - end - 8'h13: begin - /* Set addr low */ - dut_addr[7:0] <= data; - end - 8'h14: begin - /* Set addr high */ - dut_addr[12:8] <= data[4:0]; - end - 8'h15: begin - /* Set P pulse len */ - prog_pulselen <= data; - end - 8'h16: begin - /* Set E/G */ - dut_E <= data[0]; - dut_G <= data[1]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[2:0] <= zif[23:21]; - read_data[7:3] <= zif[29:25]; - end - 8'h12: begin - /* Read status */ - read_data[0] <= (prog_busy[0] != prog_busy[1]); - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, high); /* VPP */ - bufif0(zif[12], dut_addr[12], low); /* A12 */ - bufif0(zif[13], dut_addr[7], low); /* A7 */ - bufif0(zif[14], dut_addr[6], low); /* A6 */ - bufif0(zif[15], dut_addr[5], low); /* A5 */ - bufif0(zif[16], dut_addr[4], low); /* A4 */ - bufif0(zif[17], dut_addr[3], low); /* A3 */ - bufif0(zif[18], dut_addr[2], low); /* A2 */ - bufif0(zif[19], dut_addr[1], low); /* A1 */ - bufif0(zif[20], dut_addr[0], low); /* A0 */ - bufif0(zif[21], dut_data[0], !dut_G); /* Q0 */ - bufif0(zif[22], dut_data[1], !dut_G); /* Q1 */ - bufif0(zif[23], dut_data[2], !dut_G); /* Q2 */ - bufif0(zif[24], low, low); /* Vss */ - bufif0(zif[25], dut_data[3], !dut_G); /* Q3 */ - bufif0(zif[26], dut_data[4], !dut_G); /* Q4 */ - bufif0(zif[27], dut_data[5], !dut_G); /* Q5 */ - bufif0(zif[28], dut_data[6], !dut_G); /* Q6 */ - bufif0(zif[29], dut_data[7], !dut_G); /* Q7 */ - bufif0(zif[30], dut_E, low); /* E */ - bufif0(zif[31], dut_addr[10], low); /* A10 */ - bufif0(zif[32], dut_G, low); /* G */ - bufif0(zif[33], dut_addr[11], low); /* A11 */ - bufif0(zif[34], dut_addr[9], low); /* A9 */ - bufif0(zif[35], dut_addr[8], low); /* A8 */ - bufif0(zif[36], low, low); /* NC */ - bufif0(zif[37], dut_P, low); /* P */ - bufif0(zif[38], high, low); /* Vcc */ - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/m2764a/m2764a.xst b/libtoprammer/bit/src/m2764a/m2764a.xst deleted file mode 100644 index bf215df..0000000 --- a/libtoprammer/bit/src/m2764a/m2764a.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn m2764a.prj --ifmt mixed --ofn m2764a --ofmt NGC --p xc2s15-5-vq100 --top m2764a --opt_mode Speed --opt_level 1 --iuc NO --lso m2764a.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/m8c-issp/Makefile b/libtoprammer/bit/src/m8c-issp/Makefile deleted file mode 100644 index 601c3f9..0000000 --- a/libtoprammer/bit/src/m8c-issp/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=m8c-issp -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.lso b/libtoprammer/bit/src/m8c-issp/m8c-issp.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.prj b/libtoprammer/bit/src/m8c-issp/m8c-issp.prj deleted file mode 100644 index 9394251..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "m8c-issp.v" diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf b/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf deleted file mode 100644 index 17f86dc..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.ut b/libtoprammer/bit/src/m8c-issp/m8c-issp.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.v b/libtoprammer/bit/src/m8c-issp/m8c-issp.v deleted file mode 100644 index be16d49..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.v +++ /dev/null @@ -1,394 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Cypress M8C/M7C In System Serial Programmer - * FPGA bottomhalf implementation - * - * Copyright (c) 2010-2011 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0007 -`define RUNTIME_REV 16'h01 - -module m8c_issp(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - /* The M8C programmer context */ - `define ISSP_VEC_SIZE 22 /* bits */ - reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */ - reg [7:0] issp_command; /* Currently loaded command */ - reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */ - reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */ - reg [7:0] issp_count; /* General purpose counter */ - reg [3:0] issp_state; /* Statemachine */ - - /* The M8C programmer commands */ - `define ISSPCMD_NONE 0 /* No command loaded */ - `define ISSPCMD_POR 1 /* Perform a power-on-reset */ - `define ISSPCMD_PWROFF 2 /* Turn power off */ - `define ISSPCMD_EXEC 3 /* Do an "execute" transfer */ - - `define IS_BUSY (issp_busy[0] != issp_busy[1]) - `define SET_FINISHED issp_busy[1] <= issp_busy[0] - - /* The M8C device signals */ - wire sig_sdata; - wire sig_sdata_input; - wire sig_sclk; - wire sig_sclk_z; - reg dut_sdata; - reg dut_sdata_input; - reg dut_sclk; - reg dut_sclk_z; - reg dut_bitbang_disabled; - reg dut_bitbang_sdata; - reg dut_bitbang_sdata_input; - reg dut_bitbang_sclk; - reg dut_bitbang_sclk_z; - reg dut_vdd; - `define VDD_ON 1 - `define VDD_OFF 0 - `define ZIF_SDATA 22 /* SDATA ZIF pin */ - - assign low = 0; - assign high = 1; - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - `define DELAY_250NS 6 - 1 /* 250 ns */ - `define DELAY_1US 24 - 1 /* 1 us */ - `define DELAY_1MS 24000 - 1 /* 1 ms */ - `define DELAY_1P5MS 36000 - 1 /* 1.5 ms */ - `define DELAY_2MS 48000 - 1 /* 2 ms */ - - initial begin - address <= 0; - read_data <= 0; - - issp_busy <= 0; - issp_command <= 0; - issp_vector <= 0; - issp_vecbit <= 0; - issp_count <= 0; - issp_state <= 0; - - dut_sdata <= 0; - dut_sdata_input <= 1; - dut_sclk <= 0; - dut_sclk_z <= 1; - dut_vdd <= `VDD_OFF; - - dut_bitbang_disabled <= 0; - dut_bitbang_sdata <= 0; - dut_bitbang_sdata_input <= 1; - dut_bitbang_sclk <= 0; - dut_bitbang_sclk_z <= 1; - - delay_count <= 0; - end - - always @(posedge osc) begin - if (delay_count == 0 && `IS_BUSY) begin - case (issp_command) - `ISSPCMD_POR: begin - case (issp_state) - 0: begin - /* Turn on power and wait vDDwait time */ - dut_vdd <= `VDD_ON; - dut_bitbang_disabled <= 1; - dut_sclk_z <= 1; - dut_sclk <= 0; - dut_sdata_input <= 1; - delay_count <= `DELAY_1MS; /* TvDDwait */ - issp_state <= 1; - end - 1: begin - dut_sclk_z <= 0; - dut_sclk <= 0; - if (zif[`ZIF_SDATA] == 0) begin - issp_state <= 2; - issp_vecbit <= `ISSP_VEC_SIZE; - end -// delay_count <= `DELAY_250NS; - end - 2: begin - if (issp_vecbit == 0) begin - issp_state <= 4; - end else begin - /* Ok, ready to send the next bit */ - dut_sdata_input <= 0; - dut_sdata <= issp_vector[issp_vecbit - 1]; - dut_sclk <= 1; - issp_state <= 3; - end - delay_count <= `DELAY_250NS; - end - 3: begin - dut_sclk <= 0; - issp_state <= 2; - issp_vecbit <= issp_vecbit - 1; - delay_count <= `DELAY_250NS; - end - 4: begin - /* We're done. */ - `SET_FINISHED; - dut_bitbang_disabled <= 0; - dut_sclk <= 0; - dut_sdata_input <= 1; - issp_state <= 0; - end - endcase - end - `ISSPCMD_PWROFF: begin - dut_vdd <= `VDD_OFF; - dut_bitbang_disabled <= 0; - dut_sdata <= 0; - dut_sdata_input <= 1; - dut_sclk <= 0; - dut_sclk_z <= 1; - issp_state <= 0; - delay_count <= 0; - /* We're done. */ - `SET_FINISHED; - end - `ISSPCMD_EXEC: begin - case (issp_state) - 0: begin /* Init */ - dut_bitbang_disabled <= 1; - dut_sdata <= 0; - dut_sdata_input <= 1; - dut_sclk_z <= 0; - dut_sclk <= 0; - issp_count <= 10; - issp_state <= 1; - end - 1: begin /* Wait for SDATA=1 */ - if (zif[`ZIF_SDATA]) begin - issp_state <= 5; /* goto wait-for-SDATA=0 */ - end else begin - delay_count <= `DELAY_1US; - issp_count <= issp_count - 1; - issp_state <= 2; - end - end - 2: begin - if (issp_count == 0) begin - /* Timeout */ - issp_state <= 3; /* Send 33 CLKs */ - issp_count <= 33; - end else begin - issp_state <= 1; - end - end - 3: begin /* Send 33 CLKs */ - dut_sclk <= 1; - issp_count <= issp_count - 1; - delay_count <= `DELAY_250NS; - issp_state <= 4; - end - 4: begin - dut_sclk <= 0; - if (issp_count == 0) begin - /* Sent all */ - if (zif[`ZIF_SDATA]) begin - issp_state <= 5; /* goto wait-for-SDATA=0 */ - end else begin - /* goto send-50-CLKs */ - issp_state <= 6; - issp_count <= 50; - end - end else begin - issp_state <= 3; - end - delay_count <= `DELAY_250NS; - end - 5: begin /* Wait for SDATA=0 */ - if (zif[`ZIF_SDATA] == 0) begin - issp_state <= 6; - issp_count <= 50; - end else begin - issp_state <= 5; - end - delay_count <= `DELAY_250NS; - end - 6: begin /* Send 50 CLKs */ - dut_sclk <= 1; - issp_count <= issp_count - 1; - delay_count <= `DELAY_250NS; - issp_state <= 7; - end - 7: begin - dut_sclk <= 0; - if (issp_count == 0) begin - issp_state <= 8; /* done */ - end else begin - issp_state <= 6; - end - delay_count <= `DELAY_250NS; - end - 8: begin /* finish */ - /* We're done. */ - dut_bitbang_disabled <= 0; - issp_state <= 0; - `SET_FINISHED; - end - endcase - end - endcase - end else begin - if (delay_count) begin - delay_count <= delay_count - 1; - end - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Bitbanging */ - dut_bitbang_sdata <= data[0]; - dut_bitbang_sdata_input <= data[1]; - dut_bitbang_sclk <= data[2]; - dut_bitbang_sclk_z <= data[3]; - end - 8'h11: begin - /* Load and execute command */ - issp_command <= data; - issp_busy[0] <= ~issp_busy[1]; - end - 8'h12: begin - /* Load vector low */ - issp_vector[7:0] <= data; - end - 8'h13: begin - /* Load vector med */ - issp_vector[15:8] <= data; - end - 8'h14: begin - /* Load vector high */ - issp_vector[21:16] <= data[5:0]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Read status */ - read_data[0] <= issp_busy[0]; - read_data[1] <= issp_busy[1]; - - read_data[2] <= issp_state[0]; - read_data[3] <= issp_state[1]; - read_data[4] <= issp_state[2]; - - read_data[5] <= zif[`ZIF_SDATA]; - read_data[6] <= 0; - read_data[7] <= 0; - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - assign sig_sdata = dut_bitbang_disabled ? dut_sdata : dut_bitbang_sdata; - assign sig_sdata_input = dut_bitbang_disabled ? dut_sdata_input : dut_bitbang_sdata_input; - assign sig_sclk = dut_bitbang_disabled ? dut_sclk : dut_bitbang_sclk; - assign sig_sclk_z = dut_bitbang_disabled ? dut_sclk_z : dut_bitbang_sclk_z; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); /* GND */ - bufif0(zif[21], high, low); /* VDD */ - bufif0(zif[`ZIF_SDATA], sig_sdata, sig_sdata_input); /* SDATA */ - bufif0(zif[23], sig_sclk, sig_sclk_z); /* SCLK */ - bufif0(zif[24], dut_vdd, low); /* VDDen */ - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], low, low); - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], low, low); - bufif0(zif[34], low, low); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.xst b/libtoprammer/bit/src/m8c-issp/m8c-issp.xst deleted file mode 100644 index d3e62ed..0000000 --- a/libtoprammer/bit/src/m8c-issp/m8c-issp.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn m8c-issp.prj --ifmt mixed --ofn m8c-issp --ofmt NGC --p xc2s15-5-vq100 --top m8c_issp --opt_mode Area --opt_level 2 --iuc NO --lso m8c-issp.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/makefile.common b/libtoprammer/bit/src/makefile.common deleted file mode 100644 index b981bb6..0000000 --- a/libtoprammer/bit/src/makefile.common +++ /dev/null @@ -1,35 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml *.ptwx *.xrpt xlnx_auto_* - -.PHONY: all clean diff --git a/libtoprammer/bit/src/template/Makefile b/libtoprammer/bit/src/template/Makefile deleted file mode 100644 index 2631402..0000000 --- a/libtoprammer/bit/src/template/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=template -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/template/template.lso b/libtoprammer/bit/src/template/template.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/template/template.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/template/template.prj b/libtoprammer/bit/src/template/template.prj deleted file mode 100644 index 32dbdd2..0000000 --- a/libtoprammer/bit/src/template/template.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "template.v" diff --git a/libtoprammer/bit/src/template/template.ucf b/libtoprammer/bit/src/template/template.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/template/template.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/template/template.ut b/libtoprammer/bit/src/template/template.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/template/template.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/template/template.v b/libtoprammer/bit/src/template/template.v deleted file mode 100644 index 7dcba23..0000000 --- a/libtoprammer/bit/src/template/template.v +++ /dev/null @@ -1,147 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * XXXXXXXXXXXXXXXX - * FPGA bottomhalf implementation - * - * Copyright (c) YEAR NAME - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'hTODO Get an unused ID from the file "RUNTIME_IDS" -`define RUNTIME_REV 16'h01 - -module template(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - assign low = 0; - assign high = 1; - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - initial begin - address <= 0; - read_data <= 0; - delay_count <= 0; - end - - always @(posedge osc) begin - if (delay_count == 0) begin - /* TODO */ - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin /* Bulk write */ - /* TODO */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Bulk read */ - /* TODO */ - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); - bufif0(zif[21], low, low); - bufif0(zif[22], low, low); - bufif0(zif[23], low, low); - bufif0(zif[24], low, low); - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], low, low); - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], low, low); - bufif0(zif[34], low, low); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/template/template.xst b/libtoprammer/bit/src/template/template.xst deleted file mode 100644 index 00b1958..0000000 --- a/libtoprammer/bit/src/template/template.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn template.prj --ifmt mixed --ofn template --ofmt NGC --p xc2s15-5-vq100 --top template --opt_mode Speed --opt_level 1 --iuc NO --lso template.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/unitest/Makefile b/libtoprammer/bit/src/unitest/Makefile deleted file mode 100644 index 7dfd82f..0000000 --- a/libtoprammer/bit/src/unitest/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=unitest -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/unitest/unitest.lso b/libtoprammer/bit/src/unitest/unitest.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/unitest/unitest.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/unitest/unitest.prj b/libtoprammer/bit/src/unitest/unitest.prj deleted file mode 100644 index 6de4d45..0000000 --- a/libtoprammer/bit/src/unitest/unitest.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "unitest.v" diff --git a/libtoprammer/bit/src/unitest/unitest.ucf b/libtoprammer/bit/src/unitest/unitest.ucf deleted file mode 100644 index 17f86dc..0000000 --- a/libtoprammer/bit/src/unitest/unitest.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/unitest/unitest.ut b/libtoprammer/bit/src/unitest/unitest.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/unitest/unitest.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/unitest/unitest.v b/libtoprammer/bit/src/unitest/unitest.v deleted file mode 100644 index 1cbe570..0000000 --- a/libtoprammer/bit/src/unitest/unitest.v +++ /dev/null @@ -1,169 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Universal device tester - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0008 -`define RUNTIME_REV 16'h01 - -module unitest(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* ZIF pin controls */ - reg [47:0] zif_output_en; - reg [47:0] zif_output; - reg [47:0] zif_osc_en; - reg zif_osc; - - reg [24:0] osc_divider; - reg [24:0] osc_div_cnt; - - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - always @(posedge osc) begin - /* 24MHz clock */ - if (osc_div_cnt + 1 >= osc_divider) begin - osc_div_cnt <= 0; - zif_osc <= ~zif_osc; - end else begin - osc_div_cnt <= osc_div_cnt + 1; - end - end - - always @(posedge write) begin - case (address) - 8'h12: osc_divider[7:0] <= data; - 8'h13: osc_divider[15:8] <= data; - 8'h14: osc_divider[23:16] <= data; - 8'h15: osc_divider[24] <= data[0]; - - 8'h30: zif_osc_en[7:0] <= data; - 8'h31: zif_osc_en[15:8] <= data; - 8'h32: zif_osc_en[23:16] <= data; - 8'h33: zif_osc_en[31:24] <= data; - 8'h34: zif_osc_en[39:32] <= data; - 8'h35: zif_osc_en[47:40] <= data; - - 8'h50: zif_output_en[7:0] <= data; - 8'h51: zif_output_en[15:8] <= data; - 8'h52: zif_output_en[23:16] <= data; - 8'h53: zif_output_en[31:24] <= data; - 8'h54: zif_output_en[39:32] <= data; - 8'h55: zif_output_en[47:40] <= data; - - 8'h70: zif_output[7:0] <= data; - 8'h71: zif_output[15:8] <= data; - 8'h72: zif_output[23:16] <= data; - 8'h73: zif_output[31:24] <= data; - 8'h74: zif_output[39:32] <= data; - 8'h75: zif_output[47:40] <= data; - endcase - end - - always @(negedge read) begin - case (address) - 8'h30: read_data <= zif[8:1]; - 8'h31: read_data <= zif[16:9]; - 8'h32: read_data <= zif[24:17]; - 8'h33: read_data <= zif[32:25]; - 8'h34: read_data <= zif[40:33]; - 8'h35: read_data <= zif[48:41]; - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - bufif1(zif[1], zif_output[0] | (zif_osc & zif_osc_en[0]), zif_output_en[0]); - bufif1(zif[2], zif_output[1] | (zif_osc & zif_osc_en[1]), zif_output_en[1]); - bufif1(zif[3], zif_output[2] | (zif_osc & zif_osc_en[2]), zif_output_en[2]); - bufif1(zif[4], zif_output[3] | (zif_osc & zif_osc_en[3]), zif_output_en[3]); - bufif1(zif[5], zif_output[4] | (zif_osc & zif_osc_en[4]), zif_output_en[4]); - bufif1(zif[6], zif_output[5] | (zif_osc & zif_osc_en[5]), zif_output_en[5]); - bufif1(zif[7], zif_output[6] | (zif_osc & zif_osc_en[6]), zif_output_en[6]); - bufif1(zif[8], zif_output[7] | (zif_osc & zif_osc_en[7]), zif_output_en[7]); - bufif1(zif[9], zif_output[8] | (zif_osc & zif_osc_en[8]), zif_output_en[8]); - bufif1(zif[10], zif_output[9] | (zif_osc & zif_osc_en[9]), zif_output_en[9]); - bufif1(zif[11], zif_output[10] | (zif_osc & zif_osc_en[10]), zif_output_en[10]); - bufif1(zif[12], zif_output[11] | (zif_osc & zif_osc_en[11]), zif_output_en[11]); - bufif1(zif[13], zif_output[12] | (zif_osc & zif_osc_en[12]), zif_output_en[12]); - bufif1(zif[14], zif_output[13] | (zif_osc & zif_osc_en[13]), zif_output_en[13]); - bufif1(zif[15], zif_output[14] | (zif_osc & zif_osc_en[14]), zif_output_en[14]); - bufif1(zif[16], zif_output[15] | (zif_osc & zif_osc_en[15]), zif_output_en[15]); - bufif1(zif[17], zif_output[16] | (zif_osc & zif_osc_en[16]), zif_output_en[16]); - bufif1(zif[18], zif_output[17] | (zif_osc & zif_osc_en[17]), zif_output_en[17]); - bufif1(zif[19], zif_output[18] | (zif_osc & zif_osc_en[18]), zif_output_en[18]); - bufif1(zif[20], zif_output[19] | (zif_osc & zif_osc_en[19]), zif_output_en[19]); - bufif1(zif[21], zif_output[20] | (zif_osc & zif_osc_en[20]), zif_output_en[20]); - bufif1(zif[22], zif_output[21] | (zif_osc & zif_osc_en[21]), zif_output_en[21]); - bufif1(zif[23], zif_output[22] | (zif_osc & zif_osc_en[22]), zif_output_en[22]); - bufif1(zif[24], zif_output[23] | (zif_osc & zif_osc_en[23]), zif_output_en[23]); - bufif1(zif[25], zif_output[24] | (zif_osc & zif_osc_en[24]), zif_output_en[24]); - bufif1(zif[26], zif_output[25] | (zif_osc & zif_osc_en[25]), zif_output_en[25]); - bufif1(zif[27], zif_output[26] | (zif_osc & zif_osc_en[26]), zif_output_en[26]); - bufif1(zif[28], zif_output[27] | (zif_osc & zif_osc_en[27]), zif_output_en[27]); - bufif1(zif[29], zif_output[28] | (zif_osc & zif_osc_en[28]), zif_output_en[28]); - bufif1(zif[30], zif_output[29] | (zif_osc & zif_osc_en[29]), zif_output_en[29]); - bufif1(zif[31], zif_output[30] | (zif_osc & zif_osc_en[30]), zif_output_en[30]); - bufif1(zif[32], zif_output[31] | (zif_osc & zif_osc_en[31]), zif_output_en[31]); - bufif1(zif[33], zif_output[32] | (zif_osc & zif_osc_en[32]), zif_output_en[32]); - bufif1(zif[34], zif_output[33] | (zif_osc & zif_osc_en[33]), zif_output_en[33]); - bufif1(zif[35], zif_output[34] | (zif_osc & zif_osc_en[34]), zif_output_en[34]); - bufif1(zif[36], zif_output[35] | (zif_osc & zif_osc_en[35]), zif_output_en[35]); - bufif1(zif[37], zif_output[36] | (zif_osc & zif_osc_en[36]), zif_output_en[36]); - bufif1(zif[38], zif_output[37] | (zif_osc & zif_osc_en[37]), zif_output_en[37]); - bufif1(zif[39], zif_output[38] | (zif_osc & zif_osc_en[38]), zif_output_en[38]); - bufif1(zif[40], zif_output[39] | (zif_osc & zif_osc_en[39]), zif_output_en[39]); - bufif1(zif[41], zif_output[40] | (zif_osc & zif_osc_en[40]), zif_output_en[40]); - bufif1(zif[42], zif_output[41] | (zif_osc & zif_osc_en[41]), zif_output_en[41]); - bufif1(zif[43], zif_output[42] | (zif_osc & zif_osc_en[42]), zif_output_en[42]); - bufif1(zif[44], zif_output[43] | (zif_osc & zif_osc_en[43]), zif_output_en[43]); - bufif1(zif[45], zif_output[44] | (zif_osc & zif_osc_en[44]), zif_output_en[44]); - bufif1(zif[46], zif_output[45] | (zif_osc & zif_osc_en[45]), zif_output_en[45]); - bufif1(zif[47], zif_output[46] | (zif_osc & zif_osc_en[46]), zif_output_en[46]); - bufif1(zif[48], zif_output[47] | (zif_osc & zif_osc_en[47]), zif_output_en[47]); - - assign read_oe = !read && address[4]; - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/unitest/unitest.xst b/libtoprammer/bit/src/unitest/unitest.xst deleted file mode 100644 index 301cdb2..0000000 --- a/libtoprammer/bit/src/unitest/unitest.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn unitest.prj --ifmt mixed --ofn unitest --ofmt NGC --p xc2s15-5-vq100 --top unitest --opt_mode Area --opt_level 1 --iuc NO --lso unitest.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/w29ee011dip32/Makefile b/libtoprammer/bit/src/w29ee011dip32/Makefile deleted file mode 100644 index 47db19d..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -NAME:=w29ee011dip32 -SRCS:=$(NAME).v - -include ../makefile.common diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.lso b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.lso deleted file mode 100644 index b8f99f5..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.prj b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.prj deleted file mode 100644 index e0dee6b..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "w29ee011dip32.v" diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ucf b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ut b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ut deleted file mode 100644 index 009a4e6..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.v b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.v deleted file mode 100644 index 3c03bca..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.v +++ /dev/null @@ -1,311 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Winbond W29EE011 DIP32 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* The runtime ID and revision. */ -`define RUNTIME_ID 16'h0009 -`define RUNTIME_REV 16'h01 - -module w29ee011dip32(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 24MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - assign low = 0; - assign high = 1; - - /* Programmer context */ - reg [1:0] prog_busy; - reg [3:0] prog_command; - reg [3:0] prog_state; - reg [16:0] prog_addr; - parameter WRITE_BUF_SIZE = 128; - reg [7:0] write_buf[0:WRITE_BUF_SIZE-1]; - //synthesis attribute ram_style write_buf block; - reg [7:0] write_buf_count; - reg [7:0] write_buf_iter; - parameter JEDEC_BUF_SIZE = 6; - reg [7:0] jedec_addr_lo[0:JEDEC_BUF_SIZE-1]; - reg [7:0] jedec_addr_med[0:JEDEC_BUF_SIZE-1]; - reg [0:0] jedec_addr_hi[0:JEDEC_BUF_SIZE-1]; - reg [7:0] jedec_data[0:JEDEC_BUF_SIZE-1]; - reg [2:0] jedec_buf_count; - reg [2:0] jedec_buf_iter; - reg in_jedec; - reg [16:0] dut_write_addr; - reg [16:0] dut_read_addr; - wire [16:0] dut_addr; - reg [7:0] dut_jedec_data; - reg [7:0] dut_write_data; - wire [7:0] dut_data; - reg dut_ce; - reg dut_oe; - reg dut_we; - - /* Programmer commands */ - parameter CMD_WRITEBUF = 1; - - /* The delay counter. Based on the 24MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - initial begin - address <= 0; - read_data <= 0; - delay_count <= 0; - - prog_busy <= 0; - prog_command <= 0; - prog_state <= 0; - prog_addr <= 0; - write_buf_count <= 0; - write_buf_iter <= 0; - jedec_buf_count <= 0; - jedec_buf_iter <= 0; - in_jedec <= 1; - dut_write_addr <= 0; - dut_read_addr <= 0; - dut_jedec_data <= 0; - dut_write_data <= 0; - dut_ce <= 1; - dut_oe <= 1; - dut_we <= 1; - end - - `define DELAY_1US delay_count <= (24 * 1) - 1 - `define DELAY_350US delay_count <= (24 * 350) - 1 - - always @(posedge osc) begin - if (delay_count == 0) begin - if (prog_busy[0] != prog_busy[1]) begin - case (prog_command) - CMD_WRITEBUF: begin - case (prog_state) - 0: begin - in_jedec <= 1; - dut_write_addr[7:0] <= jedec_addr_lo[jedec_buf_iter]; - dut_write_addr[15:8] <= jedec_addr_med[jedec_buf_iter]; - dut_write_addr[16] <= jedec_addr_hi[jedec_buf_iter]; - dut_jedec_data <= jedec_data[jedec_buf_iter]; - dut_we <= 0; - jedec_buf_iter <= jedec_buf_iter + 1; - prog_state <= 1; - `DELAY_1US; - end - 1: begin - dut_we <= 1; - if (jedec_buf_iter == jedec_buf_count) - prog_state <= 2; /* Advance to payload */ - else - prog_state <= 0; - `DELAY_1US; - end - 2: begin - if (write_buf_count == 0) begin - /* Done. No payload. */ - prog_state <= 5; - `DELAY_350US; - end else begin - prog_state <= 3; - in_jedec <= 0; - dut_write_addr <= prog_addr; - end - end - 3: begin - dut_write_data <= write_buf[write_buf_iter]; - dut_we <= 0; - write_buf_iter <= write_buf_iter + 1; - prog_state <= 4; - `DELAY_1US; - end - 4: begin - dut_we <= 1; - if (write_buf_iter == write_buf_count) begin - prog_state <= 5; - `DELAY_350US; - end else begin - dut_write_addr <= dut_write_addr + 1; - prog_state <= 3; - `DELAY_1US; - end - end - 5: begin - /* Done. The final delay for the actual operation to - * finish is done in software. */ - jedec_buf_iter <= 0; - write_buf_iter <= 0; - prog_state <= 0; - prog_busy[1] <= prog_busy[0]; - end - endcase - end - endcase - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin /* Write to temporary write-buffer */ - write_buf[write_buf_count] <= data; - write_buf_count <= write_buf_count + 1; - end - 8'h12: begin /* Run command */ - prog_command <= data; - prog_busy[0] <= ~prog_busy[1]; - end - 8'h13: begin /* Reset temporary write-buffer count */ - jedec_buf_count <= 0; - write_buf_count <= 0; - end - 8'h14: begin /* Write start address low */ - prog_addr[7:0] <= data; - end - 8'h15: begin /* Write start address med */ - prog_addr[15:8] <= data; - end - 8'h16: begin /* Write start address high */ - prog_addr[16] <= data[0]; - end - 8'h17: begin /* Read address low */ - dut_read_addr[7:0] <= data; - end - 8'h18: begin /* Read address med */ - dut_read_addr[15:8] <= data; - end - 8'h19: begin /* Read address high */ - dut_read_addr[16] <= data[0]; - end - 8'h1A: begin /* Set #CE, #OE */ - dut_ce <= data[0]; - dut_oe <= data[1]; - end - 8'h1B: begin /* JEDEC command buffer write addr lo */ - jedec_addr_lo[jedec_buf_count] <= data; - end - 8'h1C: begin /* JEDEC command buffer write addr med */ - jedec_addr_med[jedec_buf_count] <= data; - end - 8'h1D: begin /* JEDEC command buffer write addr hi */ - jedec_addr_hi[jedec_buf_count] <= data[0]; - end - 8'h1E: begin /* JEDEC command buffer write data */ - jedec_data[jedec_buf_count] <= data; - jedec_buf_count <= jedec_buf_count + 1; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin /* Data read */ - read_data[2:0] <= zif[23:21]; - read_data[7:3] <= zif[29:25]; - end - 8'h12: begin /* Status read */ - read_data[0] <= (prog_busy[0] != prog_busy[1]); - end - - 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; - 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; - 8'hFF: read_data <= `RUNTIME_REV; - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign dut_addr = (prog_busy[0] == prog_busy[1]) ? dut_read_addr : dut_write_addr; - assign dut_data = in_jedec ? dut_jedec_data : dut_write_data; - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, high); /* NC */ - bufif0(zif[10], dut_addr[16], low); /* A16 */ - bufif0(zif[11], dut_addr[15], low); /* A15 */ - bufif0(zif[12], dut_addr[12], low); /* A12 */ - bufif0(zif[13], dut_addr[7], low); /* A7 */ - bufif0(zif[14], dut_addr[6], low); /* A6 */ - bufif0(zif[15], dut_addr[5], low); /* A5 */ - bufif0(zif[16], dut_addr[4], low); /* A4 */ - bufif0(zif[17], dut_addr[3], low); /* A3 */ - bufif0(zif[18], dut_addr[2], low); /* A2 */ - bufif0(zif[19], dut_addr[1], low); /* A1 */ - bufif0(zif[20], dut_addr[0], low); /* A0 */ - bufif0(zif[21], dut_data[0], !dut_oe); /* DQ0 */ - bufif0(zif[22], dut_data[1], !dut_oe); /* DQ1 */ - bufif0(zif[23], dut_data[2], !dut_oe); /* DQ2 */ - bufif0(zif[24], low, low); /* GND */ - bufif0(zif[25], dut_data[3], !dut_oe); /* DQ3 */ - bufif0(zif[26], dut_data[4], !dut_oe); /* DQ4 */ - bufif0(zif[27], dut_data[5], !dut_oe); /* DQ5 */ - bufif0(zif[28], dut_data[6], !dut_oe); /* DQ6 */ - bufif0(zif[29], dut_data[7], !dut_oe); /* DQ7 */ - bufif0(zif[30], dut_ce, low); /* #CE */ - bufif0(zif[31], dut_addr[10], low); /* A10 */ - bufif0(zif[32], dut_oe, low); /* #OE */ - bufif0(zif[33], dut_addr[11], low); /* A11 */ - bufif0(zif[34], dut_addr[9], low); /* A9 */ - bufif0(zif[35], dut_addr[8], low); /* A8 */ - bufif0(zif[36], dut_addr[13], low); /* A13 */ - bufif0(zif[37], dut_addr[14], low); /* A14 */ - bufif0(zif[38], low, high); /* NC */ - bufif0(zif[39], dut_we, low); /* #WE */ - bufif0(zif[40], high, low); /* VDD */ - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.xst b/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.xst deleted file mode 100644 index baa6f20..0000000 --- a/libtoprammer/bit/src/w29ee011dip32/w29ee011dip32.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn w29ee011dip32.prj --ifmt mixed --ofn w29ee011dip32 --ofmt NGC --p xc2s15-5-vq100 --top w29ee011dip32 --opt_mode Area --opt_level 2 --iuc NO --lso w29ee011dip32.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style distributed --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/unitest.bit b/libtoprammer/bit/unitest.bit deleted file mode 100644 index 88ae77c..0000000 Binary files a/libtoprammer/bit/unitest.bit and /dev/null differ diff --git a/libtoprammer/bit/w29ee011dip32.bit b/libtoprammer/bit/w29ee011dip32.bit deleted file mode 100644 index 6a6e6cb..0000000 Binary files a/libtoprammer/bit/w29ee011dip32.bit and /dev/null differ diff --git a/libtoprammer/bitfile.py b/libtoprammer/bitfile.py index b5f6e4b..0745b15 100644 --- a/libtoprammer/bitfile.py +++ b/libtoprammer/bitfile.py @@ -70,7 +70,9 @@ class Bitfile: def parseFile(self, filename): try: - data = file(filename, "rb").read() + fd = open(filename, "rb") + data = fd.read() + fd.close() except (IOError), e: raise BitfileException("Failed to read \"" + filename + "\": " + e.strerror) self.filename = filename @@ -125,7 +127,7 @@ class Bitfile: def __probeFile(fullpath): try: - file(fullpath, "rb") + open(fullpath, "rb").close() except (IOError), e: return False return True @@ -137,12 +139,13 @@ def bitfileFind(filename): if filename.startswith("/"): if __probeFile(filename): return filename - paths = ( ".", "./libtoprammer/bit", ) + paths = ( ".", "./libtoprammer/fpga", ) for path in paths: fullpath = path + "/" + filename if __probeFile(fullpath): return fullpath - fullpath = pkg_resources.resource_filename("libtoprammer", "bit/" + filename) + fullpath = pkg_resources.resource_filename("libtoprammer", + "fpga/" + filename) if __probeFile(fullpath): return fullpath return None diff --git a/libtoprammer/fpga/.gitignore b/libtoprammer/fpga/.gitignore new file mode 100644 index 0000000..f9930d5 --- /dev/null +++ b/libtoprammer/fpga/.gitignore @@ -0,0 +1 @@ +*.build.log diff --git a/libtoprammer/fpga/at27c256r.bit b/libtoprammer/fpga/at27c256r.bit new file mode 100644 index 0000000..32a8c88 Binary files /dev/null and b/libtoprammer/fpga/at27c256r.bit differ diff --git a/libtoprammer/fpga/at89c2051dip20.bit b/libtoprammer/fpga/at89c2051dip20.bit new file mode 100644 index 0000000..e7d0b7e Binary files /dev/null and b/libtoprammer/fpga/at89c2051dip20.bit differ diff --git a/libtoprammer/fpga/atmega32dip40.bit b/libtoprammer/fpga/atmega32dip40.bit new file mode 100644 index 0000000..8a9ff73 Binary files /dev/null and b/libtoprammer/fpga/atmega32dip40.bit differ diff --git a/libtoprammer/fpga/atmega8dip28.bit b/libtoprammer/fpga/atmega8dip28.bit new file mode 100644 index 0000000..445f63c Binary files /dev/null and b/libtoprammer/fpga/atmega8dip28.bit differ diff --git a/libtoprammer/fpga/attiny13dip8.bit b/libtoprammer/fpga/attiny13dip8.bit new file mode 100644 index 0000000..9278a35 Binary files /dev/null and b/libtoprammer/fpga/attiny13dip8.bit differ diff --git a/libtoprammer/fpga/attiny26dip20.bit b/libtoprammer/fpga/attiny26dip20.bit new file mode 100644 index 0000000..4b5780b Binary files /dev/null and b/libtoprammer/fpga/attiny26dip20.bit differ diff --git a/libtoprammer/fpga/build.sh b/libtoprammer/fpga/build.sh new file mode 100755 index 0000000..8149afc --- /dev/null +++ b/libtoprammer/fpga/build.sh @@ -0,0 +1,118 @@ +#!/bin/sh +# Rebuild FPGA bit files +# Copyright (c) 2010-2012 Michael Buesch +# Licensed under the GNU/GPL v2+ + +basedir="$(dirname "$0")" +[ "$(echo -n "$basedir" | cut -c1)" = "/" ] || basedir="$PWD/$basedir" + +srcdir="$basedir/src" +bindir="$basedir" + + +die() +{ + echo "$*" >&2 + exit 1 +} + +terminate() +{ + die "Interrupted." +} + +trap terminate TERM INT + +usage() +{ + echo "Usage: build.sh [OPTIONS] [TARGETS]" + echo + echo "Options:" + echo " -h|--help Show this help text" + echo " -v|--verbose Verbose build" + echo + echo "Targets:" + echo "Specify the names of the targets to build, or leave blank to rebuild all." +} + +# Parse commandline +verbose=0 +targets="/" +while [ $# -gt 0 ]; do + [ "$1" = "-h" -o "$1" = "--help" ] && { + usage + exit 0 + } + [ "$1" = "-v" -o "$1" = "--verbose" ] && { + verbose=1 + shift + continue + } + target="$1" + target="${target%.bit}" # strip .bit suffix + # Add to list + targets="${targets}${target}/" + shift +done +[ "$targets" = "/" ] && targets= + +bitparser() +{ + python "$basedir/../bitfile.py" "$@" ||\ + die "Failed to execute bitparser" +} + +should_build() # $1=target +{ + target="$1" + [ "$target" = "template" ] && return 1 + [ -z "$targets" ] && return 0 + echo "$targets" | grep -qe '/'"$target"'/' +} + +# Check if the payload of two bitfiles matches +bitfile_is_equal() # $1=file1, $2=file2 +{ + [ -r $1 -a -r $2 ] || return 1 + bitparser "$1" NOACTION # Test if bitparser works + sum1="$(bitparser "$1" GETPAYLOAD | sha1sum -b - | awk '{print $1;}')" + sum2="$(bitparser "$2" GETPAYLOAD | sha1sum -b - | awk '{print $1;}')" + [ "$sum1" = "$sum2" ] +} + +for src in $srcdir/*; do + [ -d "$src" ] || continue + + srcname="$(basename $src)" + logfile="$bindir/$srcname.build.log" + + should_build $srcname || continue + + echo "Building $srcname..." + make -C $src/ clean >/dev/null ||\ + die "FAILED to clean $srcname." + if [ $verbose -eq 0 ]; then + make -C $src/ all >$logfile || { + cat $logfile + die "FAILED to build $srcname." + } + cat $logfile | grep WARNING + else + make -C $src/ all ||\ + die "FAILED to build $srcname." + fi + + new="$src/$srcname.bit" + old="$bindir/$srcname.bit" + if bitfile_is_equal "$old" "$new"; then + echo "Bitfile for target $srcname did not change" + else + cp -f "$new" "$old" + fi + make -C $src/ clean >/dev/null ||\ + die "FAILED to clean $srcname." + rm -f $logfile +done +echo "Successfully built all images." + +exit 0 diff --git a/libtoprammer/fpga/hm62256dip28.bit b/libtoprammer/fpga/hm62256dip28.bit new file mode 100644 index 0000000..9a74c4f Binary files /dev/null and b/libtoprammer/fpga/hm62256dip28.bit differ diff --git a/libtoprammer/fpga/m24c16dip8.bit b/libtoprammer/fpga/m24c16dip8.bit new file mode 100644 index 0000000..e30149c Binary files /dev/null and b/libtoprammer/fpga/m24c16dip8.bit differ diff --git a/libtoprammer/fpga/m2764a.bit b/libtoprammer/fpga/m2764a.bit new file mode 100644 index 0000000..cf1f8b5 Binary files /dev/null and b/libtoprammer/fpga/m2764a.bit differ diff --git a/libtoprammer/fpga/m8c-issp.bit b/libtoprammer/fpga/m8c-issp.bit new file mode 100644 index 0000000..c4c95c3 Binary files /dev/null and b/libtoprammer/fpga/m8c-issp.bit differ diff --git a/libtoprammer/fpga/src/.gitignore b/libtoprammer/fpga/src/.gitignore new file mode 100644 index 0000000..d0b5749 --- /dev/null +++ b/libtoprammer/fpga/src/.gitignore @@ -0,0 +1,29 @@ +__xst/ +__ngo/ + +*.bgn +*.bit +*.bld +*.drc +*_map.map +*_map.mrp +*_map.ncd +*_map.ngm +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*_pad.csv +*_pad.txt +*.par +*.pcf +*.srp +*.unroutes +*_usage.xml +*_summary.xml +*.xpi +*.twr +*.ptwx +*.xrpt +xlnx_auto_* diff --git a/libtoprammer/fpga/src/at27c256r/Makefile b/libtoprammer/fpga/src/at27c256r/Makefile new file mode 100644 index 0000000..8c711ed --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/Makefile @@ -0,0 +1,4 @@ +NAME:=at27c256r +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.lso b/libtoprammer/fpga/src/at27c256r/at27c256r.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.prj b/libtoprammer/fpga/src/at27c256r/at27c256r.prj new file mode 100644 index 0000000..2dbbf55 --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.prj @@ -0,0 +1 @@ +verilog work "at27c256r.v" diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.ucf b/libtoprammer/fpga/src/at27c256r/at27c256r.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.ut b/libtoprammer/fpga/src/at27c256r/at27c256r.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.v b/libtoprammer/fpga/src/at27c256r/at27c256r.v new file mode 100644 index 0000000..c14b4e5 --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.v @@ -0,0 +1,206 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel AT27C256R EPROM + * FPGA bottomhalf implementation + * + * Copyright (c) 2012 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h000C +`define RUNTIME_REV 16'h01 + +module at27c256r(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* Interface to the chip */ + reg [7:0] chip_data; + reg chip_data_en; + reg [14:0] chip_addr; + reg chip_ce; /* !CE */ + reg chip_prog_ce; /* !CE prog pulse */ + reg chip_prog_en; + wire chip_ce_wire; + reg chip_oe; /* !OE */ + + assign chip_ce_wire = chip_prog_en ? chip_prog_ce : chip_ce; + + reg [1:0] prog_busy; /* busy flag */ + reg [3:0] prog_state; /* prog state */ + + wire low, high; /* Constant lo/hi */ + assign low = 0; + assign high = 1; + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + initial begin + address <= 0; + read_data <= 0; + delay_count <= 0; + chip_data <= 0; + chip_data_en <= 0; + chip_addr <= 0; + chip_ce <= 1; + chip_prog_ce <= 1; + chip_prog_en <= 0; + chip_oe <= 1; + prog_busy <= 0; + prog_state <= 0; + end + + `define SET_BUSY prog_busy[0] <= !prog_busy[1] + `define IS_BUSY prog_busy[0] != prog_busy[1] + `define FINISH prog_busy[1] <= prog_busy[0] + + `define DELAY_100US delay_count <= 2400 - 1 /* 100uS */ + + always @(posedge osc) begin + if (delay_count == 0) begin + if (`IS_BUSY) begin + case (prog_state) + 0: begin + chip_prog_ce <= 0; + prog_state <= 1; + `DELAY_100US; + end + 1: begin + chip_prog_ce <= 1; + prog_state <= 0; + `FINISH; + end + endcase + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin /* Address low write */ + chip_addr[7:0] <= data[7:0]; + end + 8'h11: begin /* Address high write */ + chip_addr[14:8] <= data[6:0]; + end + 8'h12: begin /* Data pins write */ + chip_data[7:0] <= data[7:0]; + end + 8'h13: begin /* Flags write */ + chip_data_en <= data[0]; + chip_prog_en <= data[1]; + chip_ce <= data[2]; + chip_oe <= data[3]; + end + 8'h14: begin /* Perform prog pulse */ + `SET_BUSY; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Data pins read */ + read_data[2:0] <= zif[23:21]; + read_data[7:3] <= zif[29:25]; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, high); /* VPP */ + bufif0(zif[12], chip_addr[12], low); /* A12 */ + bufif0(zif[13], chip_addr[7], low); /* A7 */ + bufif0(zif[14], chip_addr[6], low); /* A6 */ + bufif0(zif[15], chip_addr[5], low); /* A5 */ + bufif0(zif[16], chip_addr[4], low); /* A4 */ + bufif0(zif[17], chip_addr[3], low); /* A3 */ + bufif0(zif[18], chip_addr[2], low); /* A2 */ + bufif0(zif[19], chip_addr[1], low); /* A1 */ + bufif0(zif[20], chip_addr[0], low); /* A0 */ + bufif0(zif[21], chip_data[0], !chip_data_en); /* O0 */ + bufif0(zif[22], chip_data[1], !chip_data_en); /* O1 */ + bufif0(zif[23], chip_data[2], !chip_data_en); /* O2 */ + bufif0(zif[24], low, low); /* GND */ + bufif0(zif[25], chip_data[3], !chip_data_en); /* O3 */ + bufif0(zif[26], chip_data[4], !chip_data_en); /* O4 */ + bufif0(zif[27], chip_data[5], !chip_data_en); /* O5 */ + bufif0(zif[28], chip_data[6], !chip_data_en); /* O6 */ + bufif0(zif[29], chip_data[7], !chip_data_en); /* O7 */ + bufif0(zif[30], chip_ce_wire, low); /* !CE */ + bufif0(zif[31], chip_addr[10], low); /* A10 */ + bufif0(zif[32], chip_oe, low); /* !OE */ + bufif0(zif[33], chip_addr[11], low); /* A11 */ + bufif0(zif[34], chip_addr[9], low); /* A9 */ + bufif0(zif[35], chip_addr[8], low); /* A8 */ + bufif0(zif[36], chip_addr[13], low); /* A13 */ + bufif0(zif[37], chip_addr[14], low); /* A14 */ + bufif0(zif[38], high, low); /* VCC */ + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/at27c256r/at27c256r.xst b/libtoprammer/fpga/src/at27c256r/at27c256r.xst new file mode 100644 index 0000000..8a9df2b --- /dev/null +++ b/libtoprammer/fpga/src/at27c256r/at27c256r.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn at27c256r.prj +-ifmt mixed +-ofn at27c256r +-ofmt NGC +-p xc2s15-5-vq100 +-top at27c256r +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso at27c256r.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/at89c2051dip20/Makefile b/libtoprammer/fpga/src/at89c2051dip20/Makefile new file mode 100644 index 0000000..7892761 --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/Makefile @@ -0,0 +1,4 @@ +NAME:=at89c2051dip20 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.lso b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.prj b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.prj new file mode 100644 index 0000000..d1309fc --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.prj @@ -0,0 +1 @@ +verilog work "at89c2051dip20.v" diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ucf b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ut b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.v b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.v new file mode 100644 index 0000000..bc6dddb --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.v @@ -0,0 +1,274 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel AT89C2051 DIP20 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Guido + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0005 +`define RUNTIME_REV 16'h01 + +module at89c2051dip20(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + /* Programmer context */ + reg [1:0] prog_busy; + reg [3:0] prog_command; + reg [3:0] prog_state; + reg [3:0] prog_count; + reg prog_err; + + /* DUT signals */ + reg [7:0] dut_data; + reg dut_p33; + reg dut_p34; + reg dut_p35; + reg dut_p37; + reg dut_ia; /* Increment Address */ + reg dut_prog; + reg dut_vpp; + + + assign low = 0; + assign high = 1; + + initial begin + prog_busy <= 0; + prog_command <= 0; + prog_state <= 0; + prog_err <= 0; + prog_count <= 0; + dut_data <= 0; + dut_p33 <= 0; + dut_p34 <= 0; + dut_p35 <= 0; + dut_p37 <= 0; + dut_ia <= 0; + dut_prog <= 0; + dut_vpp <= 0; + end + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + always @(posedge osc) begin + if (delay_count == 0) begin + if (prog_busy[0] != prog_busy[1]) begin + /* busy0 != busy1 indicates that a command is running. + * Continue executing it... */ + case (prog_command) + 1: begin /* Set P3.2 after init */ + dut_prog <= 1; + prog_busy[1] <= prog_busy[0]; + end + 2: begin /* clear P3.2 before shutdown */ + dut_prog <= 0; + prog_busy[1] <= prog_busy[0]; + end + 3: begin /* programm byte */ + case (prog_state) + 0: begin /* pulse */ + delay_count <= 24; + dut_prog <= 0; + prog_state <= 1; + prog_err <= 0; + end + 1: begin /* raise dut_prog */ + dut_prog <= 1; + prog_state <= 2; + prog_count <= 12; + delay_count <= 2; + end + 2: begin /* wait for ready == 1 */ + if (zif[17] == 0) begin + delay_count <= 4800; /* each 200 us */ + prog_count <= prog_count - 1; + if (prog_count == 0) begin + prog_err <= 1; + prog_state <= 3; + end + end + else begin + prog_state <= 3; + delay_count <= 24; + end + end + 3: begin /* finish */ + prog_state <= 0; + prog_busy[1] <= prog_busy[0]; + end + endcase + end + 4: begin /* chip erase */ + case (prog_state) + 0: begin /* start erasing */ + delay_count <= 24000; /* 1 ms each */ + prog_count <= 10; + dut_prog <= 0; + prog_state <= 1; + prog_err <= 0; + end + 1: begin /* loop */ + prog_count <= prog_count - 1; + if (prog_count == 0) begin + dut_prog <= 1; + prog_state <= 0; + prog_busy[1] <= prog_busy[0]; + end + else begin + delay_count <= 24000; + end + end + endcase + end + 5: begin /* set dut_vpp */ + dut_vpp <= 1; + prog_busy[1] <= prog_busy[0]; + end + 6: begin /* clear dut_vpp */ + dut_vpp <= 0; + prog_busy[1] <= prog_busy[0]; + end + endcase + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h12: begin + /* Run a command. */ + prog_command <= data; + prog_busy[0] <= ~prog_busy[1]; + end + 8'h16: begin + /* Set P33, P34, P35; IA */ + dut_p33 <= data[0]; + dut_p34 <= data[1]; + dut_p35 <= data[2]; + dut_p37 <= data[2]; + dut_ia <= data[3]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[7:0] <= zif[33:26]; + end + 8'h12: begin + /* Read status */ + read_data[0] <= (prog_busy[0] != prog_busy[1]); + read_data[1] <= prog_err; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, dut_vpp); /* VPP/Reset */ + bufif0(zif[16], low, low); /* P3.0 */ + bufif0(zif[17], low, high); /* P3.1 */ + bufif0(zif[18], low, low); /* XTAL2 */ + bufif0(zif[19], dut_ia, low); /* XTAL1 */ + bufif0(zif[20], dut_prog, low); /* P3.2 */ + bufif0(zif[21], dut_p33, low); /* P3.3 */ + bufif0(zif[22], dut_p34, low); /* P3.4 */ + bufif0(zif[23], dut_p35, low); /* P3.5 */ + bufif0(zif[24], low, low); /* GND */ + bufif0(zif[25], dut_p37, low); /* P3.7 */ + bufif0(zif[26], dut_data[0], !dut_p34); /* P1.0 */ + bufif0(zif[27], dut_data[1], !dut_p34); /* P1.1 */ + bufif0(zif[28], dut_data[2], !dut_p34); /* P1.2 */ + bufif0(zif[29], dut_data[3], !dut_p34); /* P1.3 */ + bufif0(zif[30], dut_data[4], !dut_p34); /* P1.4 */ + bufif0(zif[31], dut_data[5], !dut_p34); /* P1.5 */ + bufif0(zif[32], dut_data[6], !dut_p34); /* P1.6 */ + bufif0(zif[33], dut_data[7], !dut_p34); /* P1.7 */ + bufif0(zif[34], high, low); /* VCC */ + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.xst b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.xst new file mode 100644 index 0000000..a74a8f6 --- /dev/null +++ b/libtoprammer/fpga/src/at89c2051dip20/at89c2051dip20.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn at89c2051dip20.prj +-ifmt mixed +-ofn at89c2051dip20 +-ofmt NGC +-p xc2s15-5-vq100 +-top at89c2051dip20 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso at89c2051dip20.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/atmega32dip40/Makefile b/libtoprammer/fpga/src/atmega32dip40/Makefile new file mode 100644 index 0000000..f9e5acf --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/Makefile @@ -0,0 +1,4 @@ +NAME:=atmega32dip40 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.lso b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.prj b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.prj new file mode 100644 index 0000000..7f9b373 --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.prj @@ -0,0 +1 @@ +verilog work "atmega32dip40.v" diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ucf b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ut b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v new file mode 100644 index 0000000..c95f857 --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.v @@ -0,0 +1,203 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Mega32 DIP40 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010-2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0004 +`define RUNTIME_REV 16'h01 + +module atmega32dip40(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + reg [7:0] address; + reg [7:0] read_data; + wire read_oe; + + /* Signals to/from the DUT */ + reg dut_oe, dut_wr, dut_xtal, dut_pagel; + reg dut_bs1, dut_bs2; + reg dut_xa0, dut_xa1; + reg [7:0] dut_data; + reg dut_vpp_en; + reg dut_vpp; + reg dut_vcc_en; + reg dut_vcc; + + /* Constant lo/hi */ + wire low, high; + assign low = 0; + assign high = 1; + + initial begin + address <= 0; + read_data <= 0; + dut_oe <= 0; + dut_wr <= 0; + dut_xtal <= 0; + dut_pagel <= 0; + dut_bs1 <= 0; + dut_bs2 <= 0; + dut_xa0 <= 0; + dut_xa1 <= 0; + dut_data <= 0; + dut_vpp_en <= 0; + dut_vpp <= 0; + dut_vcc_en <= 0; + dut_vcc <= 0; + end + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin /* VCC/VPP control */ + dut_vpp_en <= data[0]; + dut_vpp <= data[1]; + dut_vcc_en <= data[2]; + dut_vcc <= data[3]; + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4: begin + dut_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6: begin + dut_xa1 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + 9: begin + dut_pagel <= data[7]; + end + 10: begin + dut_bs2 <= data[7]; + end + endcase + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data <= zif[32:25]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[39]; /* RDY */ + read_data[7:1] <= 0; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], dut_pagel, low); /* PD7, PAGEL */ + bufif0(zif[6], low, high); /* PC0 */ + bufif0(zif[7], low, high); /* PC1 */ + bufif0(zif[8], low, high); /* PC2 */ + bufif0(zif[9], low, high); /* PC3 */ + bufif0(zif[10], low, high); /* PC4 */ + bufif0(zif[11], low, high); /* PC5 */ + bufif0(zif[12], low, high); /* PC6 */ + bufif0(zif[13], low, high); /* PC7 */ + bufif0(zif[14], dut_vcc, !dut_vcc_en); /* AVCC */ + bufif0(zif[15], low, low); /* GND */ + bufif0(zif[16], low, high); /* AREF */ + bufif0(zif[17], low, high); /* PA7 */ + bufif0(zif[18], low, high); /* PA6 */ + bufif0(zif[19], low, high); /* PA5 */ + bufif0(zif[20], low, high); /* PA4 */ + bufif0(zif[21], low, high); /* PA3 */ + bufif0(zif[22], low, high); /* PA2 */ + bufif0(zif[23], low, high); /* PA1 */ + bufif0(zif[24], dut_bs2, low); /* PA0, BS2 */ + bufif0(zif[25], dut_data[0], !dut_oe); /* PB0, DATA0 */ + bufif0(zif[26], dut_data[1], !dut_oe); /* PB1, DATA1 */ + bufif0(zif[27], dut_data[2], !dut_oe); /* PB2, DATA2 */ + bufif0(zif[28], dut_data[3], !dut_oe); /* PB3, DATA3 */ + bufif0(zif[29], dut_data[4], !dut_oe); /* PB4, DATA4 */ + bufif0(zif[30], dut_data[5], !dut_oe); /* PB5, DATA5 */ + bufif0(zif[31], dut_data[6], !dut_oe); /* PB6, DATA6 */ + bufif0(zif[32], dut_data[7], !dut_oe); /* PB7, DATA7 */ + bufif0(zif[33], dut_vpp, !dut_vpp_en); /* /RESET */ + bufif0(zif[34], dut_vcc, !dut_vcc_en); /* VCC */ + bufif0(zif[35], low, low); /* GND */ + bufif0(zif[36], low, high); /* XTAL2 */ + bufif0(zif[37], dut_xtal, low); /* XTAL1 */ + bufif0(zif[38], low, high); /* PD0 */ + bufif0(zif[39], low, high); /* PD1, RDY/BSY */ + bufif0(zif[40], dut_oe, low); /* PD2, /OE */ + bufif0(zif[41], dut_wr, low); /* PD3, /WR */ + bufif0(zif[42], dut_bs1, low); /* PD4, BS1 */ + bufif0(zif[43], dut_xa0, low); /* PD5, XA0 */ + bufif0(zif[44], dut_xa1, low); /* PD6, XA1 */ + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.xst b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.xst new file mode 100644 index 0000000..fe2a54d --- /dev/null +++ b/libtoprammer/fpga/src/atmega32dip40/atmega32dip40.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn atmega32dip40.prj +-ifmt mixed +-ofn atmega32dip40 +-ofmt NGC +-p xc2s15-5-vq100 +-top atmega32dip40 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso atmega32dip40.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/atmega8dip28/Makefile b/libtoprammer/fpga/src/atmega8dip28/Makefile new file mode 100644 index 0000000..e9c0e99 --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/Makefile @@ -0,0 +1,4 @@ +NAME:=atmega8dip28 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.lso b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.prj b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.prj new file mode 100644 index 0000000..25c6746 --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.prj @@ -0,0 +1 @@ +verilog work "atmega8dip28.v" diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ucf b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ucf new file mode 100644 index 0000000..7089175 --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +#NET "osc" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; \ No newline at end of file diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ut b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v new file mode 100644 index 0000000..b36f6fb --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.v @@ -0,0 +1,205 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Mega8 DIP28 + * Atmel Mega88 DIP28 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010-2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0003 +`define RUNTIME_REV 16'h01 + +module atmega8dip28(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + reg [7:0] address; + reg [7:0] read_data; + wire read_oe; + + /* Signals to/from the DUT */ + reg dut_oe, dut_wr, dut_xtal, dut_pagel; + reg dut_bs1, dut_bs2; + reg dut_xa0, dut_xa1; + reg [7:0] dut_data; + reg dut_vpp_en; + reg dut_vpp; + reg dut_vcc_en; + reg dut_vcc; + + /* Constant lo/hi */ + wire low, high; + assign low = 0; + assign high = 1; + + initial begin + address <= 0; + read_data <= 0; + dut_oe <= 0; + dut_wr <= 0; + dut_xtal <= 0; + dut_pagel <= 0; + dut_bs1 <= 0; + dut_bs2 <= 0; + dut_xa0 <= 0; + dut_xa1 <= 0; + dut_data <= 0; + dut_vpp_en <= 0; + dut_vpp <= 0; + dut_vcc_en <= 0; + dut_vcc <= 0; + end + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin /* VCC/VPP control */ + dut_vpp_en <= data[0]; + dut_vpp <= data[1]; + dut_vcc_en <= data[2]; + dut_vcc <= data[3]; + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4: begin + dut_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6: begin + dut_xa1 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + 9: begin + dut_pagel <= data[7]; + end + 10: begin + dut_bs2 <= data[7]; + end + endcase + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[5:0] <= zif[29:24]; + read_data[7:6] <= zif[34:33]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[13]; /* RDY */ + read_data[7:1] <= 0; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], dut_vpp, !dut_vpp_en); /* PC6, /RESET */ + bufif0(zif[12], low, high); /* PD0 */ + bufif0(zif[13], low, high); /* PD1, RDY/BSY */ + bufif0(zif[14], dut_oe, low); /* PD2, /OE */ + bufif0(zif[15], dut_wr, low); /* PD3, /WR */ + bufif0(zif[16], dut_bs1, low); /* PD4, BS1 */ + bufif0(zif[17], dut_vcc, !dut_vcc_en); /* VCC */ + bufif0(zif[18], low, low); /* GND */ + bufif0(zif[19], dut_xtal, low); /* PB6, XTAL1 */ + bufif0(zif[20], low, high); /* PB7, XTAL2 */ + bufif0(zif[21], dut_xa0, low); /* PD5, XA0 */ + bufif0(zif[22], dut_xa1, low); /* PD6, XA1 */ + bufif0(zif[23], dut_pagel, low); /* PD7, PAGEL */ + bufif0(zif[24], dut_data[0], !dut_oe); /* PB0, DATA0 */ + bufif0(zif[25], dut_data[1], !dut_oe); /* PB1, DATA1 */ + bufif0(zif[26], dut_data[2], !dut_oe); /* PB2, DATA2 */ + bufif0(zif[27], dut_data[3], !dut_oe); /* PB3, DATA3 */ + bufif0(zif[28], dut_data[4], !dut_oe); /* PB4, DATA4 */ + bufif0(zif[29], dut_data[5], !dut_oe); /* PB5, DATA5 */ + bufif0(zif[30], dut_vcc, !dut_vcc_en); /* AVCC */ + bufif0(zif[31], low, high); /* AREF */ + bufif0(zif[32], low, low); /* GND */ + bufif0(zif[33], dut_data[6], !dut_oe); /* PC0, DATA6 */ + bufif0(zif[34], dut_data[7], !dut_oe); /* PC1, DATA7 */ + bufif0(zif[35], dut_bs2, low); /* PC2, BS2 */ + bufif0(zif[36], low, high); /* PC3 */ + bufif0(zif[37], low, high); /* PC4 */ + bufif0(zif[38], low, high); /* PC5 */ + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.xst b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.xst new file mode 100644 index 0000000..dd040ec --- /dev/null +++ b/libtoprammer/fpga/src/atmega8dip28/atmega8dip28.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn atmega8dip28.prj +-ifmt mixed +-ofn atmega8dip28 +-ofmt NGC +-p xc2s15-5-vq100 +-top atmega8dip28 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso atmega8dip28.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/attiny13dip8/Makefile b/libtoprammer/fpga/src/attiny13dip8/Makefile new file mode 100644 index 0000000..c561e61 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/Makefile @@ -0,0 +1,4 @@ +NAME:=attiny13dip8 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.lso b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.prj b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.prj new file mode 100644 index 0000000..a77d390 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.prj @@ -0,0 +1 @@ +verilog work "attiny13dip8.v" diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ucf b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ut b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v new file mode 100644 index 0000000..44d9822 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.v @@ -0,0 +1,244 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Tiny13 DIP8 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0001 +`define RUNTIME_REV 16'h01 + +module attiny13dip8(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* Programmer context */ + reg [1:0] prog_busy; + reg [7:0] prog_command; + reg [7:0] prog_state; + reg [7:0] prog_count; + `define CMD_SENDINSTR 1 + reg dut_sdi; + reg dut_sii; + reg dut_sci_manual; + reg dut_sci_auto; + wire dut_sci; + reg dut_sdo_driven; + reg dut_sdo_value; + reg dut_rst_driven; + reg dut_rst_value; + `define DUT_SDO 33 + reg [10:0] sdi_buf; + reg [10:0] sii_buf; + reg [10:0] sdo_buf; + + wire low, high; /* Constant lo/hi */ + assign low = 0; + assign high = 1; + + initial begin + prog_busy <= 0; + prog_command <= 0; + prog_state <= 0; + prog_count <= 0; + dut_sdi <= 0; + dut_sii <= 0; + dut_sci_manual <= 0; + dut_sci_auto <= 0; + dut_sdo_driven <= 0; + dut_sdo_value <= 0; + dut_rst_driven <= 0; + dut_rst_value <= 0; + sdi_buf <= 0; + sii_buf <= 0; + sdo_buf <= 0; + end + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + `define DELAY_1US delay_count <= 24 - 1 + + always @(posedge osc) begin + if (delay_count == 0 && prog_busy[0] != prog_busy[1]) begin + case (prog_command) + `CMD_SENDINSTR: begin + case (prog_state) + 0: begin + dut_sdi <= sdi_buf[10 - prog_count]; + dut_sii <= sii_buf[10 - prog_count]; + prog_state <= 1; + `DELAY_1US; + end + 1: begin + dut_sci_auto <= 1; /* CLK hi */ + prog_state <= 2; + `DELAY_1US; + end + 2: begin + sdo_buf[10 - prog_count] <= zif[`DUT_SDO]; + prog_count <= prog_count + 1; + prog_state <= 3; + `DELAY_1US; + end + 3: begin + dut_sci_auto <= 0; /* CLK lo */ + `DELAY_1US; + if (prog_count == 11) begin + prog_state <= 0; + prog_count <= 0; + prog_busy[1] <= prog_busy[0]; /* done */ + end else begin + prog_state <= 0; + end + end + endcase + end + endcase + end else begin + if (delay_count != 0) begin + delay_count <= delay_count - 1; + end + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin /* Unused */ + end + 8'h12: begin /* Run command */ + prog_command <= data; + prog_busy[0] <= ~prog_busy[1]; + end + 8'h13: begin /* Load SDI sequence */ + sdi_buf[1:0] <= 0; + sdi_buf[9:2] <= data; + sdi_buf[10] <= 0; + end + 8'h14: begin /* Load SII sequence */ + sii_buf[1:0] <= 0; + sii_buf[9:2] <= data; + sii_buf[10] <= 0; + end + 8'h15: begin /* Set signals manually */ + dut_sci_manual <= data[0]; /* SCI */ + dut_sdo_driven <= data[1]; /* SDO drive-enable */ + dut_sdo_value <= data[2]; /* SDO drive-value */ + dut_rst_driven <= data[3]; /* RESET drive-enable */ + dut_rst_value <= data[4]; /* RESET drive-value */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Get SDO sequence high (bits 3-10) */ + read_data[7:0] <= sdo_buf[10:3]; + end + 8'h12: begin /* Read status */ + read_data[0] <= (prog_busy[0] != prog_busy[1]); /* busy */ + read_data[1] <= zif[`DUT_SDO]; /* Raw SDO pin access */ + end + 8'h13: begin /* Get SDO sequence low (bits 0-7) */ + read_data[7:0] <= sdo_buf[7:0]; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign dut_sci = (prog_busy[0] == prog_busy[1]) ? dut_sci_manual : dut_sci_auto; + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], dut_rst_value, !dut_rst_driven); /* RESET */ + bufif0(zif[16], dut_sci, low); /* SCI */ + bufif0(zif[17], low, high); /* PB4 */ + bufif0(zif[18], low, low); /* GND */ + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); + bufif0(zif[21], low, low); + bufif0(zif[22], low, low); + bufif0(zif[23], low, low); + bufif0(zif[24], low, low); + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], low, low); + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], dut_sdi, low); /* SDI */ + bufif0(zif[32], dut_sii, low); /* SII */ + bufif0(zif[33], dut_sdo_value, !dut_sdo_driven); /* SDO */ + bufif0(zif[34], high, low); /* VCC */ + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.xst b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.xst new file mode 100644 index 0000000..84d1e50 --- /dev/null +++ b/libtoprammer/fpga/src/attiny13dip8/attiny13dip8.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn attiny13dip8.prj +-ifmt mixed +-ofn attiny13dip8 +-ofmt NGC +-p xc2s15-5-vq100 +-top attiny13dip8 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso attiny13dip8.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/attiny26dip20/Makefile b/libtoprammer/fpga/src/attiny26dip20/Makefile new file mode 100644 index 0000000..4471481 --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/Makefile @@ -0,0 +1,4 @@ +NAME:=attiny26dip20 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.lso b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.prj b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.prj new file mode 100644 index 0000000..44ed439 --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.prj @@ -0,0 +1 @@ +verilog work "attiny26dip20.v" diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ucf b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ut b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.v b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.v new file mode 100644 index 0000000..b4c17aa --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.v @@ -0,0 +1,201 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Tiny26 DIP20 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010-2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0002 +`define RUNTIME_REV 16'h01 + +module attiny26dip20(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + reg [7:0] address; + reg [7:0] read_data; + wire read_oe; + + /* Signals to/from the DUT */ + reg dut_oe, dut_wr, dut_xtal, dut_pagel_bs1; + reg dut_xa0, dut_xa1_bs2; + reg [7:0] dut_data; + reg dut_vpp_en; + reg dut_vpp; + reg dut_vcc_en; + reg dut_vcc; + + /* Constant lo/hi */ + wire low, high; + assign low = 0; + assign high = 1; + + initial begin + address <= 0; + read_data <= 0; + dut_oe <= 0; + dut_wr <= 0; + dut_xtal <= 0; + dut_pagel_bs1 <= 0; + dut_xa0 <= 0; + dut_xa1_bs2 <= 0; + dut_data <= 0; + dut_vpp_en <= 0; + dut_vpp <= 0; + dut_vcc_en <= 0; + dut_vcc <= 0; + end + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin /* VCC/VPP control */ + dut_vpp_en <= data[0]; + dut_vpp <= data[1]; + dut_vcc_en <= data[2]; + dut_vcc <= data[3]; + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4, 9: begin + dut_pagel_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6, 10: begin + dut_xa1_bs2 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + endcase + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[0] <= zif[21]; + read_data[1] <= zif[20]; + read_data[2] <= zif[19]; + read_data[3] <= zif[18]; + read_data[4] <= zif[15]; + read_data[5] <= zif[14]; + read_data[6] <= zif[13]; + read_data[7] <= zif[12]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[36]; /* RDY */ + read_data[7:1] <= 0; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], dut_data[7], !dut_oe); /* PA7, DATA7 */ + bufif0(zif[13], dut_data[6], !dut_oe); /* PA6, DATA6 */ + bufif0(zif[14], dut_data[5], !dut_oe); /* PA5, DATA5 */ + bufif0(zif[15], dut_data[4], !dut_oe); /* PA4, DATA4 */ + bufif0(zif[16], dut_vcc, !dut_vcc_en); /* AVCC */ + bufif0(zif[17], low, low); /* GND */ + bufif0(zif[18], dut_data[3], !dut_oe); /* PA3, DATA3 */ + bufif0(zif[19], dut_data[2], !dut_oe); /* PA2, DATA2 */ + bufif0(zif[20], dut_data[1], !dut_oe); /* PA1, DATA1 */ + bufif0(zif[21], dut_data[0], !dut_oe); /* PA0, DATA0 */ + bufif0(zif[22], low, low); + bufif0(zif[23], low, low); + bufif0(zif[24], low, low); + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], dut_wr, low); /* PB0, /WR */ + bufif0(zif[29], dut_xa0, low); /* PB1, XA0 */ + bufif0(zif[30], dut_xa1_bs2, low); /* PB2, XA1/BS2 */ + bufif0(zif[31], dut_pagel_bs1, low); /* PB3, PAGEL/BS1 */ + bufif0(zif[32], dut_vcc, !dut_vcc_en); /* VCC */ + bufif0(zif[33], low, low); /* GND */ + bufif0(zif[34], dut_xtal, low); /* PB4, XTAL1 */ + bufif0(zif[35], dut_oe, low); /* PB5, XTAL2, /OE */ + bufif0(zif[36], low, high); /* PB6, RDY/BSY */ + bufif0(zif[37], dut_vpp, !dut_vpp_en); /* PB7, /RESET */ + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.xst b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.xst new file mode 100644 index 0000000..6ef06ea --- /dev/null +++ b/libtoprammer/fpga/src/attiny26dip20/attiny26dip20.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn attiny26dip20.prj +-ifmt mixed +-ofn attiny26dip20 +-ofmt NGC +-p xc2s15-5-vq100 +-top attiny26dip20 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso attiny26dip20.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/create.sh b/libtoprammer/fpga/src/create.sh new file mode 100755 index 0000000..7c8214c --- /dev/null +++ b/libtoprammer/fpga/src/create.sh @@ -0,0 +1,35 @@ +#!/bin/sh +# Create source template +# Copyright (c) 2010-2012 Michael Buesch +# Licensed under the GNU/GPL v2+ + +basedir="$(dirname "$0")" +[ "$(echo -n "$basedir" | cut -c1)" = "/" ] || basedir="$PWD/$basedir" + +template="$basedir/template" + +set -e + +usage() +{ + echo "Usage: create.sh TARGET_NAME" +} + +[ $# -eq 1 ] || { + usage + exit 1 +} +name="$1" + +target="$basedir/$name" + +mkdir -p "$target" +for file in $(ls "$template"); do + suffix="$(echo "$file" | cut -d. -f2)" + targetfile="$name.$suffix" + [ "$file" = "Makefile" ] && targetfile="$file" + cat "$template/$file" |\ + sed -e 's/template/'"$name"'/' > "$target/$targetfile" +done + +exit 0 diff --git a/libtoprammer/fpga/src/hm62256dip28/Makefile b/libtoprammer/fpga/src/hm62256dip28/Makefile new file mode 100644 index 0000000..93af85c --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/Makefile @@ -0,0 +1,4 @@ +NAME:=hm62256dip28 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.lso b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.prj b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.prj new file mode 100644 index 0000000..a9e7dd8 --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.prj @@ -0,0 +1 @@ +verilog work "hm62256dip28.v" diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ucf b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ucf new file mode 100644 index 0000000..8c2d654 --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +//NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ut b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v new file mode 100644 index 0000000..0cda827 --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.v @@ -0,0 +1,153 @@ +/* + * TOP2049 Open Source programming suite + * + * HM62256 SRAM + * FPGA bottomhalf implementation + * + * Copyright (c) 2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h000A +`define RUNTIME_REV 16'h01 + +module hm62256dip28(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* Chip (DUT) signals */ + reg [14:0] dut_addr; + reg [7:0] dut_data; + reg dut_ce; + reg dut_oe; + reg dut_we; + + wire low, high; /* Constant lo/hi */ + + assign low = 0; + assign high = 1; + + always @(posedge write) begin + case (address) + 8'h10: begin /* Bulk write */ + dut_data <= data; + end + 8'h11: begin /* /CE, /OE, /WE */ + dut_ce <= data[0]; + dut_oe <= data[1]; + dut_we <= data[2]; + end + 8'h12: begin /* Addr byte 0 */ + dut_addr[7:0] <= data[7:0]; + end + 8'h13: begin /* Addr byte 1 */ + dut_addr[14:8] <= data[6:0]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Bulk read */ + read_data[0] <= zif[21]; + read_data[1] <= zif[22]; + read_data[2] <= zif[23]; + read_data[3] <= zif[25]; + read_data[4] <= zif[26]; + read_data[5] <= zif[27]; + read_data[6] <= zif[28]; + read_data[7] <= zif[29]; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], dut_addr[14], low); /* A14 */ + bufif0(zif[12], dut_addr[12], low); /* A12 */ + bufif0(zif[13], dut_addr[7], low); /* A7 */ + bufif0(zif[14], dut_addr[6], low); /* A6 */ + bufif0(zif[15], dut_addr[5], low); /* A5 */ + bufif0(zif[16], dut_addr[4], low); /* A4 */ + bufif0(zif[17], dut_addr[3], low); /* A3 */ + bufif0(zif[18], dut_addr[2], low); /* A2 */ + bufif0(zif[19], dut_addr[1], low); /* A1 */ + bufif0(zif[20], dut_addr[0], low); /* A0 */ + bufif0(zif[21], dut_data[0], !dut_oe); /* DQ0 */ + bufif0(zif[22], dut_data[1], !dut_oe); /* DQ1 */ + bufif0(zif[23], dut_data[2], !dut_oe); /* DQ2 */ + bufif0(zif[24], low, low); /* GND */ + bufif0(zif[25], dut_data[3], !dut_oe); /* DQ3 */ + bufif0(zif[26], dut_data[4], !dut_oe); /* DQ4 */ + bufif0(zif[27], dut_data[5], !dut_oe); /* DQ5 */ + bufif0(zif[28], dut_data[6], !dut_oe); /* DQ6 */ + bufif0(zif[29], dut_data[7], !dut_oe); /* DQ7 */ + bufif0(zif[30], dut_ce, low); /* /CE */ + bufif0(zif[31], dut_addr[10], low); /* A10 */ + bufif0(zif[32], dut_oe, low); /* /OE */ + bufif0(zif[33], dut_addr[11], low); /* A11 */ + bufif0(zif[34], dut_addr[9], low); /* A9 */ + bufif0(zif[35], dut_addr[8], low); /* A8 */ + bufif0(zif[36], dut_addr[13], low); /* A13 */ + bufif0(zif[37], dut_we, low); /* /WE */ + bufif0(zif[38], high, low); /* VCC */ + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.xst b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.xst new file mode 100644 index 0000000..702578f --- /dev/null +++ b/libtoprammer/fpga/src/hm62256dip28/hm62256dip28.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn hm62256dip28.prj +-ifmt mixed +-ofn hm62256dip28 +-ofmt NGC +-p xc2s15-5-vq100 +-top hm62256dip28 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso hm62256dip28.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/m24c16dip8/Makefile b/libtoprammer/fpga/src/m24c16dip8/Makefile new file mode 100644 index 0000000..8cb5e97 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/Makefile @@ -0,0 +1,4 @@ +NAME:=m24c16dip8 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.lso b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.prj b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.prj new file mode 100644 index 0000000..6478642 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.prj @@ -0,0 +1 @@ +verilog work "m24c16dip8.v" diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ucf b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ucf new file mode 100644 index 0000000..a550c07 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale_in" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ut b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.v b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.v new file mode 100644 index 0000000..8120b41 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.v @@ -0,0 +1,512 @@ +/* + * TOP2049 Open Source programming suite + * + * M24C16 I2C based serial EEPROM + * FPGA bottomhalf implementation + * + * Copyright (c) 2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h000B +`define RUNTIME_REV 16'h01 + +module i2c_module(clock, scl, sda, + write_byte, read_byte, read_mode, + do_start, expect_ack, do_stop, + finished); + input clock; + output scl; + inout sda; + input [7:0] write_byte; + output [7:0] read_byte; + input read_mode; + input do_start; + input expect_ack; + input do_stop; + output finished; + + reg [7:0] start_state; + reg [7:0] data_state; + reg [7:0] ack_state; + reg [7:0] stop_state; + reg [2:0] bit_index; + + reg sda_out; + reg sda_out_en; + reg scl_out; + reg [7:0] read_byte_out; + reg finished_out; + + initial begin + start_state <= 0; + data_state <= 0; + ack_state <= 0; + stop_state <= 0; + bit_index <= 0; + + sda_out <= 0; + sda_out_en <= 0; + scl_out <= 0; + read_byte_out <= 0; + finished_out <= 0; + end + + always @(posedge clock) begin + if (do_start && start_state != 3) begin + /* Send start condition */ + finished_out <= 0; + sda_out_en <= 1; + case (start_state) + 0: begin + /* Start SCL high */ + scl_out <= 1; + sda_out <= 1; + start_state <= 1; + end + 1: begin + /* Start condition latch */ + sda_out <= 0; + start_state <= 2; + end + 2: begin + /* Start SCL low */ + scl_out <= 0; + start_state <= 3; + end + endcase + end else if (data_state != 3) begin + /* Data transfer */ + finished_out <= 0; + if (read_mode) begin /* Read */ + sda_out_en <= 0; + sda_out <= 0; + case (data_state) + 0: begin + scl_out <= 1; + data_state <= 1; + end + 1: begin + read_byte_out[7 - bit_index] <= sda; + data_state <= 2; + end + 2: begin + scl_out <= 0; + if (bit_index == 7) begin + /* Done reading byte */ + bit_index <= 0; + data_state <= 3; + end else begin + bit_index <= bit_index + 1; + data_state <= 0; + end + end + endcase + end else begin /* Write */ + sda_out_en <= 1; + case (data_state) + 0: begin + sda_out <= write_byte[7 - bit_index]; + scl_out <= 0; + data_state <= 1; + end + 1: begin + scl_out <= 1; + data_state <= 2; + end + 2: begin + scl_out <= 0; + if (bit_index == 7) begin + /* Done writing byte */ + bit_index <= 0; + data_state <= 3; + end else begin + bit_index <= bit_index + 1; + data_state <= 0; + end + end + endcase + end + end else if (expect_ack && ack_state != 2) begin + /* Wait for ACK from chip */ + finished_out <= 0; + sda_out_en <= 0; + case (ack_state) + 0: begin + scl_out <= 1; + ack_state <= 1; + end + 1: begin + scl_out <= 0; + if (sda == 0) begin + /* Got it */ + ack_state <= 2; + end else begin + ack_state <= 0; + end + end + endcase + end else if (do_stop && stop_state != 3) begin + /* Send stop condition */ + finished_out <= 0; + sda_out_en <= 1; + case (stop_state) + 0: begin + scl_out <= 1; + sda_out <= 0; + stop_state <= 1; + end + 1: begin + sda_out <= 1; + stop_state <= 2; + end + 2: begin + stop_state <= 3; + end + endcase + end else begin + /* Reset */ + start_state <= 0; + data_state <= 0; + ack_state <= 0; + stop_state <= 0; + + finished_out <= 1; + end + end + + bufif1(sda, sda_out, sda_out_en); + bufif1(scl, scl_out, 1); + bufif1(read_byte[0], read_byte_out[0], 1); + bufif1(read_byte[1], read_byte_out[1], 1); + bufif1(read_byte[2], read_byte_out[2], 1); + bufif1(read_byte[3], read_byte_out[3], 1); + bufif1(read_byte[4], read_byte_out[4], 1); + bufif1(read_byte[5], read_byte_out[5], 1); + bufif1(read_byte[6], read_byte_out[6], 1); + bufif1(read_byte[7], read_byte_out[7], 1); + bufif1(finished, finished_out, 1); +endmodule + +module m24c16dip8(data, ale_in, write, read, osc_in, zif); + inout [7:0] data; + input ale_in; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* Programmer API and statemachine */ + reg [1:0] cmd_busy; /* bit0 != bit1 >= busy */ + reg [3:0] command; + reg [7:0] data_buffer; + reg [7:0] addr_buffer; + + `define IS_BUSY (cmd_busy[0] != cmd_busy[1]) /* Is running command? */ + `define SET_FINISHED cmd_busy[1] <= cmd_busy[0] /* Set command-finished */ + + /* Programmer commands */ + parameter CMD_DEVSEL_READ = 0; + parameter CMD_DEVSEL_WRITE = 1; + parameter CMD_SETADDR = 2; + parameter CMD_DATA_READ = 3; + parameter CMD_DATA_READ_STOP = 4; + parameter CMD_DATA_WRITE = 5; + parameter CMD_DATA_WRITE_STOP = 6; + + /* Chip signals */ + reg chip_e0; /* E0 */ + reg chip_e0_en; /* E0 enable */ + reg chip_e1; /* E1 */ + reg chip_e1_en; /* E1 enable */ + reg chip_e2; /* E2 */ + reg chip_e2_en; /* E2 enable */ + reg chip_wc; /* /WC */ + parameter ZIF_SDA = 25; + parameter ZIF_SCL = 26; + + wire low, high; /* Constant lo/hi */ + assign low = 0; + assign high = 1; + + /* I2C interface */ + reg i2c_clock; + reg [7:0] i2c_write_byte; + wire [7:0] i2c_read_byte; + reg i2c_read; /* 1=> Read mode */ + reg i2c_do_start; + reg i2c_expect_ack; + reg i2c_do_stop; + wire i2c_finished; + reg [1:0] i2c_running; + + i2c_module i2c(.clock(i2c_clock), .scl(zif[ZIF_SCL]), .sda(zif[ZIF_SDA]), + .write_byte(i2c_write_byte), .read_byte(i2c_read_byte), .read_mode(i2c_read), + .do_start(i2c_do_start), .expect_ack(i2c_expect_ack), .do_stop(i2c_do_stop), + .finished(i2c_finished)); + + /* Cached data from byte read operation */ + reg [7:0] fetched_data; + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + `define DELAY_1P5US delay_count <= 36 - 1 /* 1.5 microseconds */ + + initial begin + address <= 0; + read_data <= 0; + delay_count <= 0; + + cmd_busy <= 0; + command <= 0; + data_buffer <= 0; + addr_buffer <= 0; + + chip_e0 <= 0; + chip_e0_en <= 0; + chip_e1 <= 0; + chip_e1_en <= 0; + chip_e2 <= 0; + chip_e2_en <= 0; + chip_wc <= 0; + + i2c_clock <= 0; + i2c_write_byte <= 0; + i2c_read <= 0; + i2c_do_start <= 0; + i2c_expect_ack <= 0; + i2c_do_stop <= 0; + i2c_running <= 0; + + fetched_data <= 0; + end + + always @(posedge osc) begin + if (delay_count == 0 && `IS_BUSY) begin + if (i2c_running) begin + if (i2c_finished && i2c_running == 2) begin + i2c_running <= 0; + if (i2c_read) begin + fetched_data <= i2c_read_byte; + end + `SET_FINISHED; + end else begin + i2c_running <= 2; + i2c_clock <= ~i2c_clock; + `DELAY_1P5US; + end + end else begin + case (command) + CMD_DEVSEL_READ: begin + i2c_write_byte[7] <= 1; + i2c_write_byte[6] <= 0; + i2c_write_byte[5] <= 1; + i2c_write_byte[4] <= 0; + i2c_write_byte[3] <= chip_e2; + i2c_write_byte[2] <= chip_e1; + i2c_write_byte[1] <= chip_e0; + i2c_write_byte[0] <= 1; /* Read */ + i2c_clock <= 0; + i2c_read <= 0; + i2c_do_start <= 1; + i2c_expect_ack <= 1; + i2c_do_stop <= 0; + i2c_running <= 1; + end + CMD_DEVSEL_WRITE: begin + i2c_write_byte[7] <= 1; + i2c_write_byte[6] <= 0; + i2c_write_byte[5] <= 1; + i2c_write_byte[4] <= 0; + i2c_write_byte[3] <= chip_e2; + i2c_write_byte[2] <= chip_e1; + i2c_write_byte[1] <= chip_e0; + i2c_write_byte[0] <= 0; /* Write */ + i2c_clock <= 0; + i2c_read <= 0; + i2c_do_start <= 1; + i2c_expect_ack <= 1; + i2c_do_stop <= 0; + i2c_running <= 1; + end + CMD_SETADDR: begin + i2c_write_byte <= addr_buffer; + i2c_clock <= 0; + i2c_read <= 0; + i2c_do_start <= 0; + i2c_expect_ack <= 1; + i2c_do_stop <= 0; + i2c_running <= 1; + end + CMD_DATA_READ: begin + i2c_clock <= 0; + i2c_read <= 1; + i2c_do_start <= 0; + i2c_expect_ack <= 1; + i2c_do_stop <= 0; + i2c_running <= 1; + end + CMD_DATA_READ_STOP: begin + i2c_clock <= 0; + i2c_read <= 1; + i2c_do_start <= 0; + i2c_expect_ack <= 0; + i2c_do_stop <= 1; + i2c_running <= 1; + end + CMD_DATA_WRITE: begin + i2c_write_byte <= data_buffer; + i2c_clock <= 0; + i2c_read <= 0; + i2c_do_start <= 0; + i2c_expect_ack <= 1; + i2c_do_stop <= 0; + i2c_running <= 1; + end + CMD_DATA_WRITE_STOP: begin + i2c_write_byte <= data_buffer; + i2c_clock <= 0; + i2c_read <= 0; + i2c_do_start <= 0; + i2c_expect_ack <= 1; + i2c_do_stop <= 1; + i2c_running <= 1; + end + endcase + end + end else begin + if (delay_count != 0) begin + delay_count <= delay_count - 1; + end + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin /* Run command */ + command <= data; + cmd_busy[0] <= ~cmd_busy[1]; + end + 8'h11: begin /* Write to addr buffer */ + addr_buffer[7:0] <= data[7:0]; + end + 8'h12: begin /* Write to data buffer */ + data_buffer[7:0] <= data[7:0]; + end + 8'h13: begin /* Set control pins */ + chip_e0 <= data[0]; + chip_e0_en <= data[1]; + chip_e1 <= data[2]; + chip_e1_en <= data[3]; + chip_e2 <= data[4]; + chip_e2_en <= data[5]; + chip_wc <= data[6]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Read data buffer */ + read_data <= fetched_data; + end + 8'h11: begin /* Status read */ + read_data[0] <= cmd_busy[0]; + read_data[1] <= cmd_busy[1]; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + wire ale; + IBUFG ale_ibufg(.I(ale_in), .O(ale)); + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); + bufif0(zif[21], chip_e0, !chip_e0_en); /* E0 */ + bufif0(zif[22], chip_e1, !chip_e1_en); /* E1 */ + bufif0(zif[23], chip_e2, !chip_e2_en); /* E2 */ + bufif0(zif[24], low, low); /* VSS */ +/* bufif0(zif[25], low, high); */ /* SDA; driven by i2c module. */ +/* bufif0(zif[26], low, high); */ /* SCL; driven by i2c module. */ + bufif0(zif[27], chip_wc, low); /* /WC */ + bufif0(zif[28], high, low); /* VCC */ + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], low, low); + bufif0(zif[34], low, low); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.xst b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.xst new file mode 100644 index 0000000..99287c5 --- /dev/null +++ b/libtoprammer/fpga/src/m24c16dip8/m24c16dip8.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn m24c16dip8.prj +-ifmt mixed +-ofn m24c16dip8 +-ofmt NGC +-p xc2s15-5-vq100 +-top m24c16dip8 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso m24c16dip8.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/m2764a/Makefile b/libtoprammer/fpga/src/m2764a/Makefile new file mode 100644 index 0000000..6ce9d6e --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/Makefile @@ -0,0 +1,4 @@ +NAME:=m2764a +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/m2764a/m2764a.lso b/libtoprammer/fpga/src/m2764a/m2764a.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/m2764a/m2764a.prj b/libtoprammer/fpga/src/m2764a/m2764a.prj new file mode 100644 index 0000000..25e4d2c --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.prj @@ -0,0 +1 @@ +verilog work "m2764a.v" diff --git a/libtoprammer/fpga/src/m2764a/m2764a.ucf b/libtoprammer/fpga/src/m2764a/m2764a.ucf new file mode 100644 index 0000000..17f86dc --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/m2764a/m2764a.ut b/libtoprammer/fpga/src/m2764a/m2764a.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/m2764a/m2764a.v b/libtoprammer/fpga/src/m2764a/m2764a.v new file mode 100644 index 0000000..184ca16 --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.v @@ -0,0 +1,230 @@ +/* + * TOP2049 Open Source programming suite + * + * M2764A EPROM + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0006 +`define RUNTIME_REV 16'h01 + +module m2764a(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + /* Programmer context */ + reg [1:0] prog_busy; + reg [3:0] prog_command; + reg [3:0] prog_state; + reg [7:0] prog_pulselen; + reg [7:0] prog_count; + `define PROG_PPULSE 1 + + /* DUT signals */ + reg [12:0] dut_addr; + reg [7:0] dut_data; + reg dut_E; + reg dut_P; + reg dut_G; + + assign low = 0; + assign high = 1; + + initial begin + prog_busy <= 0; + prog_command <= 0; + prog_state <= 0; + prog_pulselen <= 0; + prog_count <= 0; + dut_addr <= 0; + dut_data <= 0; + dut_E <= 1; + dut_P <= 1; + dut_G <= 1; + end + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + always @(posedge osc) begin + if (delay_count == 0) begin + if (prog_busy[0] != prog_busy[1]) begin + /* busy0 != busy1 indicates that a command is running. + * Continue executing it... */ + + case (prog_command) + `PROG_PPULSE: begin + case (prog_state) + 0: begin /* Init */ + dut_P <= 0; + prog_count <= prog_pulselen - 1; + prog_state <= 1; + delay_count <= 24000 - 2; + end + 1: begin /* Delay loop */ + if (prog_count == 0) begin + /* Done */ + dut_P <= 1; + prog_state <= 0; + prog_busy[1] <= prog_busy[0]; + end else begin + prog_state <= 2; + delay_count <= 24000 - 2; + end + end + 2: begin + prog_count <= prog_count - 1; + prog_state <= 1; + end + endcase + end + endcase + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h12: begin + /* Run a command. */ + prog_command <= data; + prog_busy[0] <= ~prog_busy[1]; + end + 8'h13: begin + /* Set addr low */ + dut_addr[7:0] <= data; + end + 8'h14: begin + /* Set addr high */ + dut_addr[12:8] <= data[4:0]; + end + 8'h15: begin + /* Set P pulse len */ + prog_pulselen <= data; + end + 8'h16: begin + /* Set E/G */ + dut_E <= data[0]; + dut_G <= data[1]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[2:0] <= zif[23:21]; + read_data[7:3] <= zif[29:25]; + end + 8'h12: begin + /* Read status */ + read_data[0] <= (prog_busy[0] != prog_busy[1]); + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, high); /* VPP */ + bufif0(zif[12], dut_addr[12], low); /* A12 */ + bufif0(zif[13], dut_addr[7], low); /* A7 */ + bufif0(zif[14], dut_addr[6], low); /* A6 */ + bufif0(zif[15], dut_addr[5], low); /* A5 */ + bufif0(zif[16], dut_addr[4], low); /* A4 */ + bufif0(zif[17], dut_addr[3], low); /* A3 */ + bufif0(zif[18], dut_addr[2], low); /* A2 */ + bufif0(zif[19], dut_addr[1], low); /* A1 */ + bufif0(zif[20], dut_addr[0], low); /* A0 */ + bufif0(zif[21], dut_data[0], !dut_G); /* Q0 */ + bufif0(zif[22], dut_data[1], !dut_G); /* Q1 */ + bufif0(zif[23], dut_data[2], !dut_G); /* Q2 */ + bufif0(zif[24], low, low); /* Vss */ + bufif0(zif[25], dut_data[3], !dut_G); /* Q3 */ + bufif0(zif[26], dut_data[4], !dut_G); /* Q4 */ + bufif0(zif[27], dut_data[5], !dut_G); /* Q5 */ + bufif0(zif[28], dut_data[6], !dut_G); /* Q6 */ + bufif0(zif[29], dut_data[7], !dut_G); /* Q7 */ + bufif0(zif[30], dut_E, low); /* E */ + bufif0(zif[31], dut_addr[10], low); /* A10 */ + bufif0(zif[32], dut_G, low); /* G */ + bufif0(zif[33], dut_addr[11], low); /* A11 */ + bufif0(zif[34], dut_addr[9], low); /* A9 */ + bufif0(zif[35], dut_addr[8], low); /* A8 */ + bufif0(zif[36], low, low); /* NC */ + bufif0(zif[37], dut_P, low); /* P */ + bufif0(zif[38], high, low); /* Vcc */ + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/m2764a/m2764a.xst b/libtoprammer/fpga/src/m2764a/m2764a.xst new file mode 100644 index 0000000..bf215df --- /dev/null +++ b/libtoprammer/fpga/src/m2764a/m2764a.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn m2764a.prj +-ifmt mixed +-ofn m2764a +-ofmt NGC +-p xc2s15-5-vq100 +-top m2764a +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso m2764a.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/m8c-issp/Makefile b/libtoprammer/fpga/src/m8c-issp/Makefile new file mode 100644 index 0000000..601c3f9 --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/Makefile @@ -0,0 +1,4 @@ +NAME:=m8c-issp +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.lso b/libtoprammer/fpga/src/m8c-issp/m8c-issp.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.prj b/libtoprammer/fpga/src/m8c-issp/m8c-issp.prj new file mode 100644 index 0000000..9394251 --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.prj @@ -0,0 +1 @@ +verilog work "m8c-issp.v" diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.ucf b/libtoprammer/fpga/src/m8c-issp/m8c-issp.ucf new file mode 100644 index 0000000..17f86dc --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.ut b/libtoprammer/fpga/src/m8c-issp/m8c-issp.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.v b/libtoprammer/fpga/src/m8c-issp/m8c-issp.v new file mode 100644 index 0000000..be16d49 --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.v @@ -0,0 +1,394 @@ +/* + * TOP2049 Open Source programming suite + * + * Cypress M8C/M7C In System Serial Programmer + * FPGA bottomhalf implementation + * + * Copyright (c) 2010-2011 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0007 +`define RUNTIME_REV 16'h01 + +module m8c_issp(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + /* The M8C programmer context */ + `define ISSP_VEC_SIZE 22 /* bits */ + reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */ + reg [7:0] issp_command; /* Currently loaded command */ + reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */ + reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */ + reg [7:0] issp_count; /* General purpose counter */ + reg [3:0] issp_state; /* Statemachine */ + + /* The M8C programmer commands */ + `define ISSPCMD_NONE 0 /* No command loaded */ + `define ISSPCMD_POR 1 /* Perform a power-on-reset */ + `define ISSPCMD_PWROFF 2 /* Turn power off */ + `define ISSPCMD_EXEC 3 /* Do an "execute" transfer */ + + `define IS_BUSY (issp_busy[0] != issp_busy[1]) + `define SET_FINISHED issp_busy[1] <= issp_busy[0] + + /* The M8C device signals */ + wire sig_sdata; + wire sig_sdata_input; + wire sig_sclk; + wire sig_sclk_z; + reg dut_sdata; + reg dut_sdata_input; + reg dut_sclk; + reg dut_sclk_z; + reg dut_bitbang_disabled; + reg dut_bitbang_sdata; + reg dut_bitbang_sdata_input; + reg dut_bitbang_sclk; + reg dut_bitbang_sclk_z; + reg dut_vdd; + `define VDD_ON 1 + `define VDD_OFF 0 + `define ZIF_SDATA 22 /* SDATA ZIF pin */ + + assign low = 0; + assign high = 1; + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + `define DELAY_250NS 6 - 1 /* 250 ns */ + `define DELAY_1US 24 - 1 /* 1 us */ + `define DELAY_1MS 24000 - 1 /* 1 ms */ + `define DELAY_1P5MS 36000 - 1 /* 1.5 ms */ + `define DELAY_2MS 48000 - 1 /* 2 ms */ + + initial begin + address <= 0; + read_data <= 0; + + issp_busy <= 0; + issp_command <= 0; + issp_vector <= 0; + issp_vecbit <= 0; + issp_count <= 0; + issp_state <= 0; + + dut_sdata <= 0; + dut_sdata_input <= 1; + dut_sclk <= 0; + dut_sclk_z <= 1; + dut_vdd <= `VDD_OFF; + + dut_bitbang_disabled <= 0; + dut_bitbang_sdata <= 0; + dut_bitbang_sdata_input <= 1; + dut_bitbang_sclk <= 0; + dut_bitbang_sclk_z <= 1; + + delay_count <= 0; + end + + always @(posedge osc) begin + if (delay_count == 0 && `IS_BUSY) begin + case (issp_command) + `ISSPCMD_POR: begin + case (issp_state) + 0: begin + /* Turn on power and wait vDDwait time */ + dut_vdd <= `VDD_ON; + dut_bitbang_disabled <= 1; + dut_sclk_z <= 1; + dut_sclk <= 0; + dut_sdata_input <= 1; + delay_count <= `DELAY_1MS; /* TvDDwait */ + issp_state <= 1; + end + 1: begin + dut_sclk_z <= 0; + dut_sclk <= 0; + if (zif[`ZIF_SDATA] == 0) begin + issp_state <= 2; + issp_vecbit <= `ISSP_VEC_SIZE; + end +// delay_count <= `DELAY_250NS; + end + 2: begin + if (issp_vecbit == 0) begin + issp_state <= 4; + end else begin + /* Ok, ready to send the next bit */ + dut_sdata_input <= 0; + dut_sdata <= issp_vector[issp_vecbit - 1]; + dut_sclk <= 1; + issp_state <= 3; + end + delay_count <= `DELAY_250NS; + end + 3: begin + dut_sclk <= 0; + issp_state <= 2; + issp_vecbit <= issp_vecbit - 1; + delay_count <= `DELAY_250NS; + end + 4: begin + /* We're done. */ + `SET_FINISHED; + dut_bitbang_disabled <= 0; + dut_sclk <= 0; + dut_sdata_input <= 1; + issp_state <= 0; + end + endcase + end + `ISSPCMD_PWROFF: begin + dut_vdd <= `VDD_OFF; + dut_bitbang_disabled <= 0; + dut_sdata <= 0; + dut_sdata_input <= 1; + dut_sclk <= 0; + dut_sclk_z <= 1; + issp_state <= 0; + delay_count <= 0; + /* We're done. */ + `SET_FINISHED; + end + `ISSPCMD_EXEC: begin + case (issp_state) + 0: begin /* Init */ + dut_bitbang_disabled <= 1; + dut_sdata <= 0; + dut_sdata_input <= 1; + dut_sclk_z <= 0; + dut_sclk <= 0; + issp_count <= 10; + issp_state <= 1; + end + 1: begin /* Wait for SDATA=1 */ + if (zif[`ZIF_SDATA]) begin + issp_state <= 5; /* goto wait-for-SDATA=0 */ + end else begin + delay_count <= `DELAY_1US; + issp_count <= issp_count - 1; + issp_state <= 2; + end + end + 2: begin + if (issp_count == 0) begin + /* Timeout */ + issp_state <= 3; /* Send 33 CLKs */ + issp_count <= 33; + end else begin + issp_state <= 1; + end + end + 3: begin /* Send 33 CLKs */ + dut_sclk <= 1; + issp_count <= issp_count - 1; + delay_count <= `DELAY_250NS; + issp_state <= 4; + end + 4: begin + dut_sclk <= 0; + if (issp_count == 0) begin + /* Sent all */ + if (zif[`ZIF_SDATA]) begin + issp_state <= 5; /* goto wait-for-SDATA=0 */ + end else begin + /* goto send-50-CLKs */ + issp_state <= 6; + issp_count <= 50; + end + end else begin + issp_state <= 3; + end + delay_count <= `DELAY_250NS; + end + 5: begin /* Wait for SDATA=0 */ + if (zif[`ZIF_SDATA] == 0) begin + issp_state <= 6; + issp_count <= 50; + end else begin + issp_state <= 5; + end + delay_count <= `DELAY_250NS; + end + 6: begin /* Send 50 CLKs */ + dut_sclk <= 1; + issp_count <= issp_count - 1; + delay_count <= `DELAY_250NS; + issp_state <= 7; + end + 7: begin + dut_sclk <= 0; + if (issp_count == 0) begin + issp_state <= 8; /* done */ + end else begin + issp_state <= 6; + end + delay_count <= `DELAY_250NS; + end + 8: begin /* finish */ + /* We're done. */ + dut_bitbang_disabled <= 0; + issp_state <= 0; + `SET_FINISHED; + end + endcase + end + endcase + end else begin + if (delay_count) begin + delay_count <= delay_count - 1; + end + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Bitbanging */ + dut_bitbang_sdata <= data[0]; + dut_bitbang_sdata_input <= data[1]; + dut_bitbang_sclk <= data[2]; + dut_bitbang_sclk_z <= data[3]; + end + 8'h11: begin + /* Load and execute command */ + issp_command <= data; + issp_busy[0] <= ~issp_busy[1]; + end + 8'h12: begin + /* Load vector low */ + issp_vector[7:0] <= data; + end + 8'h13: begin + /* Load vector med */ + issp_vector[15:8] <= data; + end + 8'h14: begin + /* Load vector high */ + issp_vector[21:16] <= data[5:0]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Read status */ + read_data[0] <= issp_busy[0]; + read_data[1] <= issp_busy[1]; + + read_data[2] <= issp_state[0]; + read_data[3] <= issp_state[1]; + read_data[4] <= issp_state[2]; + + read_data[5] <= zif[`ZIF_SDATA]; + read_data[6] <= 0; + read_data[7] <= 0; + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + assign sig_sdata = dut_bitbang_disabled ? dut_sdata : dut_bitbang_sdata; + assign sig_sdata_input = dut_bitbang_disabled ? dut_sdata_input : dut_bitbang_sdata_input; + assign sig_sclk = dut_bitbang_disabled ? dut_sclk : dut_bitbang_sclk; + assign sig_sclk_z = dut_bitbang_disabled ? dut_sclk_z : dut_bitbang_sclk_z; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); /* GND */ + bufif0(zif[21], high, low); /* VDD */ + bufif0(zif[`ZIF_SDATA], sig_sdata, sig_sdata_input); /* SDATA */ + bufif0(zif[23], sig_sclk, sig_sclk_z); /* SCLK */ + bufif0(zif[24], dut_vdd, low); /* VDDen */ + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], low, low); + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], low, low); + bufif0(zif[34], low, low); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/m8c-issp/m8c-issp.xst b/libtoprammer/fpga/src/m8c-issp/m8c-issp.xst new file mode 100644 index 0000000..d3e62ed --- /dev/null +++ b/libtoprammer/fpga/src/m8c-issp/m8c-issp.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn m8c-issp.prj +-ifmt mixed +-ofn m8c-issp +-ofmt NGC +-p xc2s15-5-vq100 +-top m8c_issp +-opt_mode Area +-opt_level 2 +-iuc NO +-lso m8c-issp.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/makefile.common b/libtoprammer/fpga/src/makefile.common new file mode 100644 index 0000000..b981bb6 --- /dev/null +++ b/libtoprammer/fpga/src/makefile.common @@ -0,0 +1,35 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml *.ptwx *.xrpt xlnx_auto_* + +.PHONY: all clean diff --git a/libtoprammer/fpga/src/template/Makefile b/libtoprammer/fpga/src/template/Makefile new file mode 100644 index 0000000..2631402 --- /dev/null +++ b/libtoprammer/fpga/src/template/Makefile @@ -0,0 +1,4 @@ +NAME:=template +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/template/template.lso b/libtoprammer/fpga/src/template/template.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/template/template.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/template/template.prj b/libtoprammer/fpga/src/template/template.prj new file mode 100644 index 0000000..32dbdd2 --- /dev/null +++ b/libtoprammer/fpga/src/template/template.prj @@ -0,0 +1 @@ +verilog work "template.v" diff --git a/libtoprammer/fpga/src/template/template.ucf b/libtoprammer/fpga/src/template/template.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/template/template.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/template/template.ut b/libtoprammer/fpga/src/template/template.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/template/template.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/template/template.v b/libtoprammer/fpga/src/template/template.v new file mode 100644 index 0000000..7dcba23 --- /dev/null +++ b/libtoprammer/fpga/src/template/template.v @@ -0,0 +1,147 @@ +/* + * TOP2049 Open Source programming suite + * + * XXXXXXXXXXXXXXXX + * FPGA bottomhalf implementation + * + * Copyright (c) YEAR NAME + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'hTODO Get an unused ID from the file "RUNTIME_IDS" +`define RUNTIME_REV 16'h01 + +module template(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + assign low = 0; + assign high = 1; + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + initial begin + address <= 0; + read_data <= 0; + delay_count <= 0; + end + + always @(posedge osc) begin + if (delay_count == 0) begin + /* TODO */ + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin /* Bulk write */ + /* TODO */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Bulk read */ + /* TODO */ + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); + bufif0(zif[21], low, low); + bufif0(zif[22], low, low); + bufif0(zif[23], low, low); + bufif0(zif[24], low, low); + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], low, low); + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], low, low); + bufif0(zif[34], low, low); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/template/template.xst b/libtoprammer/fpga/src/template/template.xst new file mode 100644 index 0000000..00b1958 --- /dev/null +++ b/libtoprammer/fpga/src/template/template.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn template.prj +-ifmt mixed +-ofn template +-ofmt NGC +-p xc2s15-5-vq100 +-top template +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso template.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/unitest/Makefile b/libtoprammer/fpga/src/unitest/Makefile new file mode 100644 index 0000000..7dfd82f --- /dev/null +++ b/libtoprammer/fpga/src/unitest/Makefile @@ -0,0 +1,4 @@ +NAME:=unitest +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/unitest/unitest.lso b/libtoprammer/fpga/src/unitest/unitest.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/unitest/unitest.prj b/libtoprammer/fpga/src/unitest/unitest.prj new file mode 100644 index 0000000..6de4d45 --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.prj @@ -0,0 +1 @@ +verilog work "unitest.v" diff --git a/libtoprammer/fpga/src/unitest/unitest.ucf b/libtoprammer/fpga/src/unitest/unitest.ucf new file mode 100644 index 0000000..17f86dc --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/unitest/unitest.ut b/libtoprammer/fpga/src/unitest/unitest.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/unitest/unitest.v b/libtoprammer/fpga/src/unitest/unitest.v new file mode 100644 index 0000000..1cbe570 --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.v @@ -0,0 +1,169 @@ +/* + * TOP2049 Open Source programming suite + * + * Universal device tester + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0008 +`define RUNTIME_REV 16'h01 + +module unitest(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* ZIF pin controls */ + reg [47:0] zif_output_en; + reg [47:0] zif_output; + reg [47:0] zif_osc_en; + reg zif_osc; + + reg [24:0] osc_divider; + reg [24:0] osc_div_cnt; + + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + always @(posedge osc) begin + /* 24MHz clock */ + if (osc_div_cnt + 1 >= osc_divider) begin + osc_div_cnt <= 0; + zif_osc <= ~zif_osc; + end else begin + osc_div_cnt <= osc_div_cnt + 1; + end + end + + always @(posedge write) begin + case (address) + 8'h12: osc_divider[7:0] <= data; + 8'h13: osc_divider[15:8] <= data; + 8'h14: osc_divider[23:16] <= data; + 8'h15: osc_divider[24] <= data[0]; + + 8'h30: zif_osc_en[7:0] <= data; + 8'h31: zif_osc_en[15:8] <= data; + 8'h32: zif_osc_en[23:16] <= data; + 8'h33: zif_osc_en[31:24] <= data; + 8'h34: zif_osc_en[39:32] <= data; + 8'h35: zif_osc_en[47:40] <= data; + + 8'h50: zif_output_en[7:0] <= data; + 8'h51: zif_output_en[15:8] <= data; + 8'h52: zif_output_en[23:16] <= data; + 8'h53: zif_output_en[31:24] <= data; + 8'h54: zif_output_en[39:32] <= data; + 8'h55: zif_output_en[47:40] <= data; + + 8'h70: zif_output[7:0] <= data; + 8'h71: zif_output[15:8] <= data; + 8'h72: zif_output[23:16] <= data; + 8'h73: zif_output[31:24] <= data; + 8'h74: zif_output[39:32] <= data; + 8'h75: zif_output[47:40] <= data; + endcase + end + + always @(negedge read) begin + case (address) + 8'h30: read_data <= zif[8:1]; + 8'h31: read_data <= zif[16:9]; + 8'h32: read_data <= zif[24:17]; + 8'h33: read_data <= zif[32:25]; + 8'h34: read_data <= zif[40:33]; + 8'h35: read_data <= zif[48:41]; + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + bufif1(zif[1], zif_output[0] | (zif_osc & zif_osc_en[0]), zif_output_en[0]); + bufif1(zif[2], zif_output[1] | (zif_osc & zif_osc_en[1]), zif_output_en[1]); + bufif1(zif[3], zif_output[2] | (zif_osc & zif_osc_en[2]), zif_output_en[2]); + bufif1(zif[4], zif_output[3] | (zif_osc & zif_osc_en[3]), zif_output_en[3]); + bufif1(zif[5], zif_output[4] | (zif_osc & zif_osc_en[4]), zif_output_en[4]); + bufif1(zif[6], zif_output[5] | (zif_osc & zif_osc_en[5]), zif_output_en[5]); + bufif1(zif[7], zif_output[6] | (zif_osc & zif_osc_en[6]), zif_output_en[6]); + bufif1(zif[8], zif_output[7] | (zif_osc & zif_osc_en[7]), zif_output_en[7]); + bufif1(zif[9], zif_output[8] | (zif_osc & zif_osc_en[8]), zif_output_en[8]); + bufif1(zif[10], zif_output[9] | (zif_osc & zif_osc_en[9]), zif_output_en[9]); + bufif1(zif[11], zif_output[10] | (zif_osc & zif_osc_en[10]), zif_output_en[10]); + bufif1(zif[12], zif_output[11] | (zif_osc & zif_osc_en[11]), zif_output_en[11]); + bufif1(zif[13], zif_output[12] | (zif_osc & zif_osc_en[12]), zif_output_en[12]); + bufif1(zif[14], zif_output[13] | (zif_osc & zif_osc_en[13]), zif_output_en[13]); + bufif1(zif[15], zif_output[14] | (zif_osc & zif_osc_en[14]), zif_output_en[14]); + bufif1(zif[16], zif_output[15] | (zif_osc & zif_osc_en[15]), zif_output_en[15]); + bufif1(zif[17], zif_output[16] | (zif_osc & zif_osc_en[16]), zif_output_en[16]); + bufif1(zif[18], zif_output[17] | (zif_osc & zif_osc_en[17]), zif_output_en[17]); + bufif1(zif[19], zif_output[18] | (zif_osc & zif_osc_en[18]), zif_output_en[18]); + bufif1(zif[20], zif_output[19] | (zif_osc & zif_osc_en[19]), zif_output_en[19]); + bufif1(zif[21], zif_output[20] | (zif_osc & zif_osc_en[20]), zif_output_en[20]); + bufif1(zif[22], zif_output[21] | (zif_osc & zif_osc_en[21]), zif_output_en[21]); + bufif1(zif[23], zif_output[22] | (zif_osc & zif_osc_en[22]), zif_output_en[22]); + bufif1(zif[24], zif_output[23] | (zif_osc & zif_osc_en[23]), zif_output_en[23]); + bufif1(zif[25], zif_output[24] | (zif_osc & zif_osc_en[24]), zif_output_en[24]); + bufif1(zif[26], zif_output[25] | (zif_osc & zif_osc_en[25]), zif_output_en[25]); + bufif1(zif[27], zif_output[26] | (zif_osc & zif_osc_en[26]), zif_output_en[26]); + bufif1(zif[28], zif_output[27] | (zif_osc & zif_osc_en[27]), zif_output_en[27]); + bufif1(zif[29], zif_output[28] | (zif_osc & zif_osc_en[28]), zif_output_en[28]); + bufif1(zif[30], zif_output[29] | (zif_osc & zif_osc_en[29]), zif_output_en[29]); + bufif1(zif[31], zif_output[30] | (zif_osc & zif_osc_en[30]), zif_output_en[30]); + bufif1(zif[32], zif_output[31] | (zif_osc & zif_osc_en[31]), zif_output_en[31]); + bufif1(zif[33], zif_output[32] | (zif_osc & zif_osc_en[32]), zif_output_en[32]); + bufif1(zif[34], zif_output[33] | (zif_osc & zif_osc_en[33]), zif_output_en[33]); + bufif1(zif[35], zif_output[34] | (zif_osc & zif_osc_en[34]), zif_output_en[34]); + bufif1(zif[36], zif_output[35] | (zif_osc & zif_osc_en[35]), zif_output_en[35]); + bufif1(zif[37], zif_output[36] | (zif_osc & zif_osc_en[36]), zif_output_en[36]); + bufif1(zif[38], zif_output[37] | (zif_osc & zif_osc_en[37]), zif_output_en[37]); + bufif1(zif[39], zif_output[38] | (zif_osc & zif_osc_en[38]), zif_output_en[38]); + bufif1(zif[40], zif_output[39] | (zif_osc & zif_osc_en[39]), zif_output_en[39]); + bufif1(zif[41], zif_output[40] | (zif_osc & zif_osc_en[40]), zif_output_en[40]); + bufif1(zif[42], zif_output[41] | (zif_osc & zif_osc_en[41]), zif_output_en[41]); + bufif1(zif[43], zif_output[42] | (zif_osc & zif_osc_en[42]), zif_output_en[42]); + bufif1(zif[44], zif_output[43] | (zif_osc & zif_osc_en[43]), zif_output_en[43]); + bufif1(zif[45], zif_output[44] | (zif_osc & zif_osc_en[44]), zif_output_en[44]); + bufif1(zif[46], zif_output[45] | (zif_osc & zif_osc_en[45]), zif_output_en[45]); + bufif1(zif[47], zif_output[46] | (zif_osc & zif_osc_en[46]), zif_output_en[46]); + bufif1(zif[48], zif_output[47] | (zif_osc & zif_osc_en[47]), zif_output_en[47]); + + assign read_oe = !read && address[4]; + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/unitest/unitest.xst b/libtoprammer/fpga/src/unitest/unitest.xst new file mode 100644 index 0000000..301cdb2 --- /dev/null +++ b/libtoprammer/fpga/src/unitest/unitest.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn unitest.prj +-ifmt mixed +-ofn unitest +-ofmt NGC +-p xc2s15-5-vq100 +-top unitest +-opt_mode Area +-opt_level 1 +-iuc NO +-lso unitest.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/src/w29ee011dip32/Makefile b/libtoprammer/fpga/src/w29ee011dip32/Makefile new file mode 100644 index 0000000..47db19d --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/Makefile @@ -0,0 +1,4 @@ +NAME:=w29ee011dip32 +SRCS:=$(NAME).v + +include ../makefile.common diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.lso b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.prj b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.prj new file mode 100644 index 0000000..e0dee6b --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.prj @@ -0,0 +1 @@ +verilog work "w29ee011dip32.v" diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ucf b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ut b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.v b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.v new file mode 100644 index 0000000..3c03bca --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.v @@ -0,0 +1,311 @@ +/* + * TOP2049 Open Source programming suite + * + * Winbond W29EE011 DIP32 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* The runtime ID and revision. */ +`define RUNTIME_ID 16'h0009 +`define RUNTIME_REV 16'h01 + +module w29ee011dip32(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 24MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + assign low = 0; + assign high = 1; + + /* Programmer context */ + reg [1:0] prog_busy; + reg [3:0] prog_command; + reg [3:0] prog_state; + reg [16:0] prog_addr; + parameter WRITE_BUF_SIZE = 128; + reg [7:0] write_buf[0:WRITE_BUF_SIZE-1]; + //synthesis attribute ram_style write_buf block; + reg [7:0] write_buf_count; + reg [7:0] write_buf_iter; + parameter JEDEC_BUF_SIZE = 6; + reg [7:0] jedec_addr_lo[0:JEDEC_BUF_SIZE-1]; + reg [7:0] jedec_addr_med[0:JEDEC_BUF_SIZE-1]; + reg [0:0] jedec_addr_hi[0:JEDEC_BUF_SIZE-1]; + reg [7:0] jedec_data[0:JEDEC_BUF_SIZE-1]; + reg [2:0] jedec_buf_count; + reg [2:0] jedec_buf_iter; + reg in_jedec; + reg [16:0] dut_write_addr; + reg [16:0] dut_read_addr; + wire [16:0] dut_addr; + reg [7:0] dut_jedec_data; + reg [7:0] dut_write_data; + wire [7:0] dut_data; + reg dut_ce; + reg dut_oe; + reg dut_we; + + /* Programmer commands */ + parameter CMD_WRITEBUF = 1; + + /* The delay counter. Based on the 24MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + initial begin + address <= 0; + read_data <= 0; + delay_count <= 0; + + prog_busy <= 0; + prog_command <= 0; + prog_state <= 0; + prog_addr <= 0; + write_buf_count <= 0; + write_buf_iter <= 0; + jedec_buf_count <= 0; + jedec_buf_iter <= 0; + in_jedec <= 1; + dut_write_addr <= 0; + dut_read_addr <= 0; + dut_jedec_data <= 0; + dut_write_data <= 0; + dut_ce <= 1; + dut_oe <= 1; + dut_we <= 1; + end + + `define DELAY_1US delay_count <= (24 * 1) - 1 + `define DELAY_350US delay_count <= (24 * 350) - 1 + + always @(posedge osc) begin + if (delay_count == 0) begin + if (prog_busy[0] != prog_busy[1]) begin + case (prog_command) + CMD_WRITEBUF: begin + case (prog_state) + 0: begin + in_jedec <= 1; + dut_write_addr[7:0] <= jedec_addr_lo[jedec_buf_iter]; + dut_write_addr[15:8] <= jedec_addr_med[jedec_buf_iter]; + dut_write_addr[16] <= jedec_addr_hi[jedec_buf_iter]; + dut_jedec_data <= jedec_data[jedec_buf_iter]; + dut_we <= 0; + jedec_buf_iter <= jedec_buf_iter + 1; + prog_state <= 1; + `DELAY_1US; + end + 1: begin + dut_we <= 1; + if (jedec_buf_iter == jedec_buf_count) + prog_state <= 2; /* Advance to payload */ + else + prog_state <= 0; + `DELAY_1US; + end + 2: begin + if (write_buf_count == 0) begin + /* Done. No payload. */ + prog_state <= 5; + `DELAY_350US; + end else begin + prog_state <= 3; + in_jedec <= 0; + dut_write_addr <= prog_addr; + end + end + 3: begin + dut_write_data <= write_buf[write_buf_iter]; + dut_we <= 0; + write_buf_iter <= write_buf_iter + 1; + prog_state <= 4; + `DELAY_1US; + end + 4: begin + dut_we <= 1; + if (write_buf_iter == write_buf_count) begin + prog_state <= 5; + `DELAY_350US; + end else begin + dut_write_addr <= dut_write_addr + 1; + prog_state <= 3; + `DELAY_1US; + end + end + 5: begin + /* Done. The final delay for the actual operation to + * finish is done in software. */ + jedec_buf_iter <= 0; + write_buf_iter <= 0; + prog_state <= 0; + prog_busy[1] <= prog_busy[0]; + end + endcase + end + endcase + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin /* Write to temporary write-buffer */ + write_buf[write_buf_count] <= data; + write_buf_count <= write_buf_count + 1; + end + 8'h12: begin /* Run command */ + prog_command <= data; + prog_busy[0] <= ~prog_busy[1]; + end + 8'h13: begin /* Reset temporary write-buffer count */ + jedec_buf_count <= 0; + write_buf_count <= 0; + end + 8'h14: begin /* Write start address low */ + prog_addr[7:0] <= data; + end + 8'h15: begin /* Write start address med */ + prog_addr[15:8] <= data; + end + 8'h16: begin /* Write start address high */ + prog_addr[16] <= data[0]; + end + 8'h17: begin /* Read address low */ + dut_read_addr[7:0] <= data; + end + 8'h18: begin /* Read address med */ + dut_read_addr[15:8] <= data; + end + 8'h19: begin /* Read address high */ + dut_read_addr[16] <= data[0]; + end + 8'h1A: begin /* Set #CE, #OE */ + dut_ce <= data[0]; + dut_oe <= data[1]; + end + 8'h1B: begin /* JEDEC command buffer write addr lo */ + jedec_addr_lo[jedec_buf_count] <= data; + end + 8'h1C: begin /* JEDEC command buffer write addr med */ + jedec_addr_med[jedec_buf_count] <= data; + end + 8'h1D: begin /* JEDEC command buffer write addr hi */ + jedec_addr_hi[jedec_buf_count] <= data[0]; + end + 8'h1E: begin /* JEDEC command buffer write data */ + jedec_data[jedec_buf_count] <= data; + jedec_buf_count <= jedec_buf_count + 1; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin /* Data read */ + read_data[2:0] <= zif[23:21]; + read_data[7:3] <= zif[29:25]; + end + 8'h12: begin /* Status read */ + read_data[0] <= (prog_busy[0] != prog_busy[1]); + end + + 8'hFD: read_data <= `RUNTIME_ID & 16'hFF; + 8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF; + 8'hFF: read_data <= `RUNTIME_REV; + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign dut_addr = (prog_busy[0] == prog_busy[1]) ? dut_read_addr : dut_write_addr; + assign dut_data = in_jedec ? dut_jedec_data : dut_write_data; + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, high); /* NC */ + bufif0(zif[10], dut_addr[16], low); /* A16 */ + bufif0(zif[11], dut_addr[15], low); /* A15 */ + bufif0(zif[12], dut_addr[12], low); /* A12 */ + bufif0(zif[13], dut_addr[7], low); /* A7 */ + bufif0(zif[14], dut_addr[6], low); /* A6 */ + bufif0(zif[15], dut_addr[5], low); /* A5 */ + bufif0(zif[16], dut_addr[4], low); /* A4 */ + bufif0(zif[17], dut_addr[3], low); /* A3 */ + bufif0(zif[18], dut_addr[2], low); /* A2 */ + bufif0(zif[19], dut_addr[1], low); /* A1 */ + bufif0(zif[20], dut_addr[0], low); /* A0 */ + bufif0(zif[21], dut_data[0], !dut_oe); /* DQ0 */ + bufif0(zif[22], dut_data[1], !dut_oe); /* DQ1 */ + bufif0(zif[23], dut_data[2], !dut_oe); /* DQ2 */ + bufif0(zif[24], low, low); /* GND */ + bufif0(zif[25], dut_data[3], !dut_oe); /* DQ3 */ + bufif0(zif[26], dut_data[4], !dut_oe); /* DQ4 */ + bufif0(zif[27], dut_data[5], !dut_oe); /* DQ5 */ + bufif0(zif[28], dut_data[6], !dut_oe); /* DQ6 */ + bufif0(zif[29], dut_data[7], !dut_oe); /* DQ7 */ + bufif0(zif[30], dut_ce, low); /* #CE */ + bufif0(zif[31], dut_addr[10], low); /* A10 */ + bufif0(zif[32], dut_oe, low); /* #OE */ + bufif0(zif[33], dut_addr[11], low); /* A11 */ + bufif0(zif[34], dut_addr[9], low); /* A9 */ + bufif0(zif[35], dut_addr[8], low); /* A8 */ + bufif0(zif[36], dut_addr[13], low); /* A13 */ + bufif0(zif[37], dut_addr[14], low); /* A14 */ + bufif0(zif[38], low, high); /* NC */ + bufif0(zif[39], dut_we, low); /* #WE */ + bufif0(zif[40], high, low); /* VDD */ + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.xst b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.xst new file mode 100644 index 0000000..baa6f20 --- /dev/null +++ b/libtoprammer/fpga/src/w29ee011dip32/w29ee011dip32.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn w29ee011dip32.prj +-ifmt mixed +-ofn w29ee011dip32 +-ofmt NGC +-p xc2s15-5-vq100 +-top w29ee011dip32 +-opt_mode Area +-opt_level 2 +-iuc NO +-lso w29ee011dip32.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style distributed +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/fpga/unitest.bit b/libtoprammer/fpga/unitest.bit new file mode 100644 index 0000000..88ae77c Binary files /dev/null and b/libtoprammer/fpga/unitest.bit differ diff --git a/libtoprammer/fpga/w29ee011dip32.bit b/libtoprammer/fpga/w29ee011dip32.bit new file mode 100644 index 0000000..6a6e6cb Binary files /dev/null and b/libtoprammer/fpga/w29ee011dip32.bit differ diff --git a/setup.py b/setup.py index ab3c133..fd573c7 100755 --- a/setup.py +++ b/setup.py @@ -10,6 +10,6 @@ setup( name = "toprammer", author_email = "m@bues.ch", url = "http://bues.ch/cms/hacking/toprammer.html", packages = [ "libtoprammer", "libtoprammer/top2049", "libtoprammer/chips" ], - package_data = { "libtoprammer" : [ "bit/*.bit", "icons/*.png", ], }, + package_data = { "libtoprammer" : [ "fpga/*.bit", "icons/*.png", ], }, scripts = [ "toprammer", "toprammer-gui", "toprammer-layout", ], ) -- cgit v1.2.3