From dfa3c5fe7109ba7d5d4c7e80298e486b81457563 Mon Sep 17 00:00:00 2001 From: Michael Buesch Date: Sun, 21 Feb 2010 19:31:16 +0100 Subject: Add setup.py Signed-off-by: Michael Buesch --- .gitignore | 2 + README | 14 +- bit/.gitignore | 1 - bit/atmega32dip40.bit | Bin 24790 -> 0 bytes bit/atmega88dip28.bit | Bin 24790 -> 0 bytes bit/atmega8dip28.bit | Bin 24789 -> 0 bytes bit/build.sh | 112 ----- bit/m2764a.bit | Bin 24783 -> 0 bytes bit/m8c-issp.bit | Bin 24785 -> 0 bytes bit/src/.gitignore | 26 -- bit/src/atmega32dip40/Makefile | 37 -- bit/src/atmega32dip40/atmega32dip40.lso | 1 - bit/src/atmega32dip40/atmega32dip40.prj | 1 - bit/src/atmega32dip40/atmega32dip40.ucf | 62 --- bit/src/atmega32dip40/atmega32dip40.ut | 29 -- bit/src/atmega32dip40/atmega32dip40.v | 202 -------- bit/src/atmega32dip40/atmega32dip40.xst | 57 --- bit/src/atmega88dip28/Makefile | 37 -- bit/src/atmega88dip28/atmega88dip28.lso | 1 - bit/src/atmega88dip28/atmega88dip28.prj | 1 - bit/src/atmega88dip28/atmega88dip28.ucf | 62 --- bit/src/atmega88dip28/atmega88dip28.ut | 29 -- bit/src/atmega88dip28/atmega88dip28.v | 203 -------- bit/src/atmega88dip28/atmega88dip28.xst | 57 --- bit/src/atmega8dip28/Makefile | 37 -- bit/src/atmega8dip28/atmega8dip28.lso | 1 - bit/src/atmega8dip28/atmega8dip28.prj | 1 - bit/src/atmega8dip28/atmega8dip28.ucf | 65 --- bit/src/atmega8dip28/atmega8dip28.ut | 29 -- bit/src/atmega8dip28/atmega8dip28.v | 202 -------- bit/src/atmega8dip28/atmega8dip28.xst | 57 --- bit/src/create.sh | 29 -- bit/src/m2764a/Makefile | 37 -- bit/src/m2764a/m2764a.lso | 1 - bit/src/m2764a/m2764a.prj | 1 - bit/src/m2764a/m2764a.ucf | 65 --- bit/src/m2764a/m2764a.ut | 29 -- bit/src/m2764a/m2764a.v | 246 ---------- bit/src/m2764a/m2764a.xst | 57 --- bit/src/m8c-issp/Makefile | 37 -- bit/src/m8c-issp/m8c-issp.lso | 1 - bit/src/m8c-issp/m8c-issp.prj | 1 - bit/src/m8c-issp/m8c-issp.ucf | 65 --- bit/src/m8c-issp/m8c-issp.ut | 29 -- bit/src/m8c-issp/m8c-issp.v | 417 ----------------- bit/src/m8c-issp/m8c-issp.xst | 57 --- bit/src/template/Makefile | 37 -- bit/src/template/template.lso | 1 - bit/src/template/template.prj | 1 - bit/src/template/template.ucf | 62 --- bit/src/template/template.ut | 29 -- bit/src/template/template.v | 158 ------- bit/src/template/template.xst | 57 --- bit/src/unitest/Makefile | 37 -- bit/src/unitest/unitest.lso | 1 - bit/src/unitest/unitest.prj | 1 - bit/src/unitest/unitest.ucf | 65 --- bit/src/unitest/unitest.ut | 29 -- bit/src/unitest/unitest.v | 180 -------- bit/src/unitest/unitest.xst | 57 --- bit/unitest.bit | Bin 24784 -> 0 bytes bitfile.py | 162 ------- chip.py | 149 ------ chip_atmega32dip40.py | 41 -- chip_atmega88dip28.py | 40 -- chip_atmega8dip28.py | 40 -- chip_atmega_common.py | 511 --------------------- chip_m2764a.py | 161 ------- chip_m8cissp.py | 347 -------------- chip_unitest.py | 93 ---- libtoprammer/__init__.py | 1 + libtoprammer/bit/.gitignore | 1 + libtoprammer/bit/atmega32dip40.bit | Bin 0 -> 24790 bytes libtoprammer/bit/atmega88dip28.bit | Bin 0 -> 24790 bytes libtoprammer/bit/atmega8dip28.bit | Bin 0 -> 24789 bytes libtoprammer/bit/build.sh | 112 +++++ libtoprammer/bit/m2764a.bit | Bin 0 -> 24783 bytes libtoprammer/bit/m8c-issp.bit | Bin 0 -> 24785 bytes libtoprammer/bit/src/.gitignore | 26 ++ libtoprammer/bit/src/atmega32dip40/Makefile | 37 ++ .../bit/src/atmega32dip40/atmega32dip40.lso | 1 + .../bit/src/atmega32dip40/atmega32dip40.prj | 1 + .../bit/src/atmega32dip40/atmega32dip40.ucf | 62 +++ .../bit/src/atmega32dip40/atmega32dip40.ut | 29 ++ libtoprammer/bit/src/atmega32dip40/atmega32dip40.v | 202 ++++++++ .../bit/src/atmega32dip40/atmega32dip40.xst | 57 +++ libtoprammer/bit/src/atmega88dip28/Makefile | 37 ++ .../bit/src/atmega88dip28/atmega88dip28.lso | 1 + .../bit/src/atmega88dip28/atmega88dip28.prj | 1 + .../bit/src/atmega88dip28/atmega88dip28.ucf | 62 +++ .../bit/src/atmega88dip28/atmega88dip28.ut | 29 ++ libtoprammer/bit/src/atmega88dip28/atmega88dip28.v | 203 ++++++++ .../bit/src/atmega88dip28/atmega88dip28.xst | 57 +++ libtoprammer/bit/src/atmega8dip28/Makefile | 37 ++ libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso | 1 + libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj | 1 + libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf | 65 +++ libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut | 29 ++ libtoprammer/bit/src/atmega8dip28/atmega8dip28.v | 202 ++++++++ libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst | 57 +++ libtoprammer/bit/src/create.sh | 29 ++ libtoprammer/bit/src/m2764a/Makefile | 37 ++ libtoprammer/bit/src/m2764a/m2764a.lso | 1 + libtoprammer/bit/src/m2764a/m2764a.prj | 1 + libtoprammer/bit/src/m2764a/m2764a.ucf | 65 +++ libtoprammer/bit/src/m2764a/m2764a.ut | 29 ++ libtoprammer/bit/src/m2764a/m2764a.v | 246 ++++++++++ libtoprammer/bit/src/m2764a/m2764a.xst | 57 +++ libtoprammer/bit/src/m8c-issp/Makefile | 37 ++ libtoprammer/bit/src/m8c-issp/m8c-issp.lso | 1 + libtoprammer/bit/src/m8c-issp/m8c-issp.prj | 1 + libtoprammer/bit/src/m8c-issp/m8c-issp.ucf | 65 +++ libtoprammer/bit/src/m8c-issp/m8c-issp.ut | 29 ++ libtoprammer/bit/src/m8c-issp/m8c-issp.v | 417 +++++++++++++++++ libtoprammer/bit/src/m8c-issp/m8c-issp.xst | 57 +++ libtoprammer/bit/src/template/Makefile | 37 ++ libtoprammer/bit/src/template/template.lso | 1 + libtoprammer/bit/src/template/template.prj | 1 + libtoprammer/bit/src/template/template.ucf | 62 +++ libtoprammer/bit/src/template/template.ut | 29 ++ libtoprammer/bit/src/template/template.v | 158 +++++++ libtoprammer/bit/src/template/template.xst | 57 +++ libtoprammer/bit/src/unitest/Makefile | 37 ++ libtoprammer/bit/src/unitest/unitest.lso | 1 + libtoprammer/bit/src/unitest/unitest.prj | 1 + libtoprammer/bit/src/unitest/unitest.ucf | 65 +++ libtoprammer/bit/src/unitest/unitest.ut | 29 ++ libtoprammer/bit/src/unitest/unitest.v | 180 ++++++++ libtoprammer/bit/src/unitest/unitest.xst | 57 +++ libtoprammer/bit/unitest.bit | Bin 0 -> 24784 bytes libtoprammer/bitfile.py | 165 +++++++ libtoprammer/chip.py | 149 ++++++ libtoprammer/chip_atmega32dip40.py | 41 ++ libtoprammer/chip_atmega88dip28.py | 40 ++ libtoprammer/chip_atmega8dip28.py | 40 ++ libtoprammer/chip_atmega_common.py | 511 +++++++++++++++++++++ libtoprammer/chip_m2764a.py | 161 +++++++ libtoprammer/chip_m8cissp.py | 347 ++++++++++++++ libtoprammer/chip_unitest.py | 93 ++++ libtoprammer/top2049/__init__.py | 1 + libtoprammer/top2049/gnd_layouts.py | 66 +++ libtoprammer/top2049/shiftreg_layout.py | 98 ++++ libtoprammer/top2049/vccx_layouts.py | 150 ++++++ libtoprammer/top2049/vpp_layouts.py | 159 +++++++ libtoprammer/toprammer_main.py | 436 ++++++++++++++++++ libtoprammer/util.py | 75 +++ makerelease.sh | 7 +- setup.py | 15 + top2049/__init__.py | 1 - top2049/gnd_layouts.py | 66 --- top2049/shiftreg_layout.py | 98 ---- top2049/vccx_layouts.py | 150 ------ top2049/vpp_layouts.py | 159 ------- toprammer | 2 +- toprammer-unitest | 2 +- toprammer_main.py | 436 ------------------ util.py | 75 --- 157 files changed, 5661 insertions(+), 5637 deletions(-) delete mode 100644 bit/.gitignore delete mode 100644 bit/atmega32dip40.bit delete mode 100644 bit/atmega88dip28.bit delete mode 100644 bit/atmega8dip28.bit delete mode 100755 bit/build.sh delete mode 100644 bit/m2764a.bit delete mode 100644 bit/m8c-issp.bit delete mode 100644 bit/src/.gitignore delete mode 100644 bit/src/atmega32dip40/Makefile delete mode 100644 bit/src/atmega32dip40/atmega32dip40.lso delete mode 100644 bit/src/atmega32dip40/atmega32dip40.prj delete mode 100644 bit/src/atmega32dip40/atmega32dip40.ucf delete mode 100644 bit/src/atmega32dip40/atmega32dip40.ut delete mode 100644 bit/src/atmega32dip40/atmega32dip40.v delete mode 100644 bit/src/atmega32dip40/atmega32dip40.xst delete mode 100644 bit/src/atmega88dip28/Makefile delete mode 100644 bit/src/atmega88dip28/atmega88dip28.lso delete mode 100644 bit/src/atmega88dip28/atmega88dip28.prj delete mode 100644 bit/src/atmega88dip28/atmega88dip28.ucf delete mode 100644 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mode 100644 libtoprammer/bitfile.py create mode 100644 libtoprammer/chip.py create mode 100644 libtoprammer/chip_atmega32dip40.py create mode 100644 libtoprammer/chip_atmega88dip28.py create mode 100644 libtoprammer/chip_atmega8dip28.py create mode 100644 libtoprammer/chip_atmega_common.py create mode 100644 libtoprammer/chip_m2764a.py create mode 100644 libtoprammer/chip_m8cissp.py create mode 100644 libtoprammer/chip_unitest.py create mode 100644 libtoprammer/top2049/__init__.py create mode 100644 libtoprammer/top2049/gnd_layouts.py create mode 100644 libtoprammer/top2049/shiftreg_layout.py create mode 100644 libtoprammer/top2049/vccx_layouts.py create mode 100644 libtoprammer/top2049/vpp_layouts.py create mode 100644 libtoprammer/toprammer_main.py create mode 100644 libtoprammer/util.py create mode 100755 setup.py delete mode 100644 top2049/__init__.py delete mode 100644 top2049/gnd_layouts.py delete mode 100644 top2049/shiftreg_layout.py delete mode 100644 top2049/vccx_layouts.py delete mode 100644 top2049/vpp_layouts.py delete mode 100644 toprammer_main.py delete mode 100644 util.py diff --git a/.gitignore b/.gitignore index ace8ff8..42f0873 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ +build + *~ *.swp *.pyc diff --git a/README b/README index 35a5dbe..0351f0a 100644 --- a/README +++ b/README @@ -26,7 +26,9 @@ m2764a EPROM | uncertain | === INSTALLATION === -No installation is required. Just execute the "toprammer" file. +Just execute + python setup.py install +as root inside of the toprammer distribution package's root directory. @@ -35,8 +37,8 @@ No installation is required. Just execute the "toprammer" file. A .BIT file is always needed to do operations on the inserted chip. The .BIT file must match the chip. For example, do do operations on an Atmel Mega8 DIP microcontroller, the atmega8dip28.bit file is needed. -Prebuilt .BIT files can be found in the "bit/" subdirectory. -Sourcecode for these .BIT files is located in "bit/src/". +Prebuilt .BIT files can be found in the "libtoprammer/bit/" subdirectory. +Sourcecode for these .BIT files is located in "libtoprammer/bit/src/". However, the full path to the .BIT file doesn't need to be specified to the toprammer tool. If you just pass the chip-name, toprammer will search for a matching .BIT file in some standard search paths. @@ -76,12 +78,12 @@ for the top-half. --- Bottom-half FPGA implementation --- To create a new sourcecode template fileset for a new chip, go to the -bit/src/ subdirectory and execute the "create.sh" script: +libtoprammer/bit/src/ subdirectory and execute the "create.sh" script: ./create.sh name_of_chip where "name_of_chip" is the name of the new chip. -Now go to bit/src/name_of_chip/ and implement the bottom-half algorithm +Now go to libtoprammer/bit/src/name_of_chip/ and implement the bottom-half algorithm in the name_of_chip.v Verilog file. -To build the .BIT file from the Verilog sources, go to the bit/ directory +To build the .BIT file from the Verilog sources, go to the libtoprammer/bit/ directory and execute: ./build.sh name_of_chip (if you omit the chipname, all chips will be rebuilt). diff --git a/bit/.gitignore b/bit/.gitignore deleted file mode 100644 index f9930d5..0000000 --- a/bit/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.build.log diff --git a/bit/atmega32dip40.bit b/bit/atmega32dip40.bit deleted file mode 100644 index d7a163d..0000000 Binary files a/bit/atmega32dip40.bit and /dev/null differ diff --git a/bit/atmega88dip28.bit b/bit/atmega88dip28.bit deleted file mode 100644 index 02f0964..0000000 Binary files a/bit/atmega88dip28.bit and /dev/null differ diff --git a/bit/atmega8dip28.bit b/bit/atmega8dip28.bit deleted file mode 100644 index 8fb5846..0000000 Binary files a/bit/atmega8dip28.bit and /dev/null differ diff --git a/bit/build.sh b/bit/build.sh deleted file mode 100755 index b1dc553..0000000 --- a/bit/build.sh +++ /dev/null @@ -1,112 +0,0 @@ -#!/bin/bash -# Rebuild FPGA bit files -# Copyright (c) 2010 Michael Buesch -# Licensed under the GNU/GPL v2+ - -basedir="$PWD/$(dirname $0)" -srcdir="$basedir/src" -bindir="$basedir" -bitparser="python $basedir/../bitfile.py" - -function terminate -{ - echo "Interrupted." - exit 1 -} - -trap terminate TERM INT - -function usage -{ - echo "Usage: build.sh [OPTIONS] [TARGETS]" - echo - echo "Options:" - echo " -h|--help Show this help text" - echo " -v|--verbose Verbose build" - echo - echo "Targets:" - echo "Specify the names of the targets to build, or leave blank to rebuild all." -} - -# Parse commandline -verbose=0 -nr_targets=0 -while [ $# -gt 0 ]; do - if [ "$1" = "-h" -o "$1" = "--help" ]; then - usage - exit 0 - fi - if [ "$1" = "-v" -o "$1" = "--verbose" ]; then - verbose=1 - shift - continue - fi - targets[nr_targets]="$1" - let nr_targets=nr_targets+1 - shift -done - -function should_build # $1=target -{ - target="$1" - [ "$target" = "template" ] && return 1 - [ $nr_targets -eq 0 ] && return 0 - let end=nr_targets-1 - for i in $(seq 0 $end); do - [ ${targets[i]} = "$target" ] && return 0 - done - return 1 -} - -# Check if the payload of two bitfiles matches -function bitfile_is_equal # $1=file1, $2=file2 -{ - [ -r $1 -a -r $2 ] || return 1 - sum1="$($bitparser $1 GETPAYLOAD | sha1sum - | cut -d' ' -f1)" - sum2="$($bitparser $2 GETPAYLOAD | sha1sum - | cut -d' ' -f1)" - [ "$sum1" = "$sum2" ] -} - -for src in $srcdir/*; do - [ -d "$src" ] || continue - - srcname="$(basename $src)" - logfile="$bindir/$srcname.build.log" - - should_build $srcname || continue - - echo "Building $srcname..." - make -C $src/ clean >/dev/null - if [ $? -ne 0 ]; then - echo "FAILED to clean $srcname." - exit 1 - fi - if [ $verbose -eq 0 ]; then - make -C $src/ all >$logfile - if [ $? -ne 0 ]; then - cat $logfile - echo "FAILED to build $srcname." - exit 1 - fi - cat $logfile | grep WARNING - else - make -C $src/ all - fi - - new="$src/$srcname.bit" - old="$bindir/$srcname.bit" - if bitfile_is_equal "$old" "$new"; then - echo "Bitfile for target $srcname did not change" - else - cp -f "$new" "$old" - fi - make -C $src/ clean >/dev/null - if [ $? -ne 0 ]; then - echo "FAILED to clean $srcname." - exit 1 - fi - rm -f $logfile -done -echo "Successfully built all images." - -exit 0 diff --git a/bit/m2764a.bit b/bit/m2764a.bit deleted file mode 100644 index 3f1fc18..0000000 Binary files a/bit/m2764a.bit and /dev/null differ diff --git a/bit/m8c-issp.bit b/bit/m8c-issp.bit deleted file mode 100644 index fc1f354..0000000 Binary files a/bit/m8c-issp.bit and /dev/null differ diff --git a/bit/src/.gitignore b/bit/src/.gitignore deleted file mode 100644 index e5aa91f..0000000 --- a/bit/src/.gitignore +++ /dev/null @@ -1,26 +0,0 @@ -__xst/ -__ngo/ - -*.bgn -*.bit -*.bld -*.drc -*_map.map -*_map.mrp -*_map.ncd -*_map.ngm -*.ncd -*.ngc -*.ngd -*.ngr -*.pad -*_pad.csv -*_pad.txt -*.par -*.pcf -*.srp -*.unroutes -*_usage.xml -*_summary.xml -*.xpi -*.twr diff --git a/bit/src/atmega32dip40/Makefile b/bit/src/atmega32dip40/Makefile deleted file mode 100644 index 62d5914..0000000 --- a/bit/src/atmega32dip40/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = atmega32dip40 -SRCS = $(NAME).v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/atmega32dip40/atmega32dip40.lso b/bit/src/atmega32dip40/atmega32dip40.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/atmega32dip40/atmega32dip40.prj b/bit/src/atmega32dip40/atmega32dip40.prj deleted file mode 100644 index 7f9b373..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "atmega32dip40.v" diff --git a/bit/src/atmega32dip40/atmega32dip40.ucf b/bit/src/atmega32dip40/atmega32dip40.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/atmega32dip40/atmega32dip40.ut b/bit/src/atmega32dip40/atmega32dip40.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/atmega32dip40/atmega32dip40.v b/bit/src/atmega32dip40/atmega32dip40.v deleted file mode 100644 index f547d71..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.v +++ /dev/null @@ -1,202 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Mega32 DIP40 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module atmega32dip40(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - // Read output-enable - wire read_oe; - // Signals to/from the DUT - reg dut_oe, dut_wr, dut_xtal, dut_pagel; - reg dut_bs1, dut_bs2; - reg dut_xa0, dut_xa1; - reg [7:0] dut_data; - // Cached address value - reg [7:0] address; - // Cached read data - reg [7:0] read_data; - // Constant lo/hi - wire low, high; - - assign low = 0; - assign high = 1; - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin - /* Nothing */ - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4: begin - dut_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6: begin - dut_xa1 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - 9: begin - dut_pagel <= data[7]; - end - 10: begin - dut_bs2 <= data[7]; - end - endcase - end - 8'h1B: begin - /* Nothing */ - end - 8'h1D: begin - /* Nothing */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data <= zif[32:25]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[39]; /* RDY */ - read_data[7:1] <= 0; - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], dut_pagel, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); - bufif0(zif[21], low, low); - bufif0(zif[22], low, low); - bufif0(zif[23], low, low); - bufif0(zif[24], dut_bs2, low); - bufif0(zif[25], dut_data[0], !dut_oe); - bufif0(zif[26], dut_data[1], !dut_oe); - bufif0(zif[27], dut_data[2], !dut_oe); - bufif0(zif[28], dut_data[3], !dut_oe); - bufif0(zif[29], dut_data[4], !dut_oe); - bufif0(zif[30], dut_data[5], !dut_oe); - bufif0(zif[31], dut_data[6], !dut_oe); - bufif0(zif[32], dut_data[7], !dut_oe); - bufif0(zif[33], low, high); - bufif0(zif[34], low, high); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], dut_xtal, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, high); - bufif0(zif[40], dut_oe, low); - bufif0(zif[41], dut_wr, low); - bufif0(zif[42], dut_bs1, low); - bufif0(zif[43], dut_xa0, low); - bufif0(zif[44], dut_xa1, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/atmega32dip40/atmega32dip40.xst b/bit/src/atmega32dip40/atmega32dip40.xst deleted file mode 100644 index fe2a54d..0000000 --- a/bit/src/atmega32dip40/atmega32dip40.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn atmega32dip40.prj --ifmt mixed --ofn atmega32dip40 --ofmt NGC --p xc2s15-5-vq100 --top atmega32dip40 --opt_mode Speed --opt_level 1 --iuc NO --lso atmega32dip40.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/atmega88dip28/Makefile b/bit/src/atmega88dip28/Makefile deleted file mode 100644 index ae94a7f..0000000 --- a/bit/src/atmega88dip28/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = atmega88dip28 -SRCS = $(NAME).v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/atmega88dip28/atmega88dip28.lso b/bit/src/atmega88dip28/atmega88dip28.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/atmega88dip28/atmega88dip28.prj b/bit/src/atmega88dip28/atmega88dip28.prj deleted file mode 100644 index 295880e..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "atmega88dip28.v" diff --git a/bit/src/atmega88dip28/atmega88dip28.ucf b/bit/src/atmega88dip28/atmega88dip28.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/atmega88dip28/atmega88dip28.ut b/bit/src/atmega88dip28/atmega88dip28.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/atmega88dip28/atmega88dip28.v b/bit/src/atmega88dip28/atmega88dip28.v deleted file mode 100644 index 2898dbb..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.v +++ /dev/null @@ -1,203 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Mega88 DIP28 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module atmega88dip28(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - // Read output-enable - wire read_oe; - // Signals to/from the DUT - reg dut_oe, dut_wr, dut_xtal, dut_pagel; - reg dut_bs1, dut_bs2; - reg dut_xa0, dut_xa1; - reg [7:0] dut_data; - // Cached address value - reg [7:0] address; - // Cached read data - reg [7:0] read_data; - // Constant lo/hi - wire low, high; - - assign low = 0; - assign high = 1; - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin - /* Nothing */ - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4: begin - dut_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6: begin - dut_xa1 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - 9: begin - dut_pagel <= data[7]; - end - 10: begin - dut_bs2 <= data[7]; - end - endcase - end - 8'h1B: begin - /* Nothing */ - end - 8'h1D: begin - /* Nothing */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[5:0] <= zif[29:24]; - read_data[7:6] <= zif[34:33]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[13]; /* RDY */ - read_data[7:1] <= 0; - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, high); - bufif0(zif[14], dut_oe, low); - bufif0(zif[15], dut_wr, low); - bufif0(zif[16], dut_bs1, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], dut_xtal, low); - bufif0(zif[20], low, low); - bufif0(zif[21], dut_xa0, low); - bufif0(zif[22], dut_xa1, low); - bufif0(zif[23], dut_pagel, low); - bufif0(zif[24], dut_data[0], !dut_oe); - bufif0(zif[25], dut_data[1], !dut_oe); - bufif0(zif[26], dut_data[2], !dut_oe); - bufif0(zif[27], dut_data[3], !dut_oe); - bufif0(zif[28], dut_data[4], !dut_oe); - bufif0(zif[29], dut_data[5], !dut_oe); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], dut_data[6], !dut_oe); - bufif0(zif[34], dut_data[7], !dut_oe); - bufif0(zif[35], dut_bs2, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/atmega88dip28/atmega88dip28.xst b/bit/src/atmega88dip28/atmega88dip28.xst deleted file mode 100644 index e602aa8..0000000 --- a/bit/src/atmega88dip28/atmega88dip28.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn atmega88dip28.prj --ifmt mixed --ofn atmega88dip28 --ofmt NGC --p xc2s15-5-vq100 --top atmega88dip28 --opt_mode Speed --opt_level 1 --iuc NO --lso atmega88dip28.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/atmega8dip28/Makefile b/bit/src/atmega8dip28/Makefile deleted file mode 100644 index 0a8ce4b..0000000 --- a/bit/src/atmega8dip28/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = atmega8dip28 -SRCS = atmega8dip28.v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/atmega8dip28/atmega8dip28.lso b/bit/src/atmega8dip28/atmega8dip28.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/atmega8dip28/atmega8dip28.prj b/bit/src/atmega8dip28/atmega8dip28.prj deleted file mode 100644 index 25c6746..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "atmega8dip28.v" diff --git a/bit/src/atmega8dip28/atmega8dip28.ucf b/bit/src/atmega8dip28/atmega8dip28.ucf deleted file mode 100644 index 7089175..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -#NET "osc" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; \ No newline at end of file diff --git a/bit/src/atmega8dip28/atmega8dip28.ut b/bit/src/atmega8dip28/atmega8dip28.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/atmega8dip28/atmega8dip28.v b/bit/src/atmega8dip28/atmega8dip28.v deleted file mode 100644 index 77b4d7f..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.v +++ /dev/null @@ -1,202 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Atmel Mega8 DIP28 - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ -module atmega8dip28(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - // Read output-enable - wire read_oe; - // Signals to/from the DUT - reg dut_oe, dut_wr, dut_xtal, dut_pagel; - reg dut_bs1, dut_bs2; - reg dut_xa0, dut_xa1; - reg [7:0] dut_data; - // Cached address value - reg [7:0] address; - // Cached read data - reg [7:0] read_data; - // Constant lo/hi - wire low, high; - - assign low = 0; - assign high = 1; - - always @(negedge ale) begin - address <= data; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h11: begin - /* Nothing */ - end - 8'h12: begin - /* Control pin access */ - case (data[6:0]) - 1: begin - /* Unused */ - end - 2: begin - dut_oe <= data[7]; - end - 3: begin - dut_wr <= data[7]; - end - 4: begin - dut_bs1 <= data[7]; - end - 5: begin - dut_xa0 <= data[7]; - end - 6: begin - dut_xa1 <= data[7]; - end - 7: begin - dut_xtal <= data[7]; - end - 8: begin - /* Unused */ - end - 9: begin - dut_pagel <= data[7]; - end - 10: begin - dut_bs2 <= data[7]; - end - endcase - end - 8'h1B: begin - /* Nothing */ - end - 8'h1D: begin - /* Nothing */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[5:0] <= zif[29:24]; - read_data[7:6] <= zif[34:33]; - end - 8'h12: begin - /* Status read */ - read_data[0] <= zif[13]; /* RDY */ - read_data[7:1] <= 0; - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, high); - bufif0(zif[12], low, low); - bufif0(zif[13], low, high); - bufif0(zif[14], dut_oe, low); - bufif0(zif[15], dut_wr, low); - bufif0(zif[16], dut_bs1, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], dut_xtal, low); - bufif0(zif[20], low, low); - bufif0(zif[21], dut_xa0, low); - bufif0(zif[22], dut_xa1, low); - bufif0(zif[23], dut_pagel, low); - bufif0(zif[24], dut_data[0], !dut_oe); - bufif0(zif[25], dut_data[1], !dut_oe); - bufif0(zif[26], dut_data[2], !dut_oe); - bufif0(zif[27], dut_data[3], !dut_oe); - bufif0(zif[28], dut_data[4], !dut_oe); - bufif0(zif[29], dut_data[5], !dut_oe); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], dut_data[6], !dut_oe); - bufif0(zif[34], dut_data[7], !dut_oe); - bufif0(zif[35], dut_bs2, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/atmega8dip28/atmega8dip28.xst b/bit/src/atmega8dip28/atmega8dip28.xst deleted file mode 100644 index dd040ec..0000000 --- a/bit/src/atmega8dip28/atmega8dip28.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn atmega8dip28.prj --ifmt mixed --ofn atmega8dip28 --ofmt NGC --p xc2s15-5-vq100 --top atmega8dip28 --opt_mode Speed --opt_level 1 --iuc NO --lso atmega8dip28.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/create.sh b/bit/src/create.sh deleted file mode 100755 index cce46db..0000000 --- a/bit/src/create.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash - -basedir="$PWD/$(dirname $0)" -template="$basedir/template" - -set -e - -function usage -{ - echo "Usage: create.sh TARGET_NAME" -} - -if [ $# -ne 1 ]; then - usage - exit 1 -fi -name="$1" - -target="$basedir/$name" - -mkdir -p "$target" -for file in $(ls $template); do - suffix="$(echo $file | cut -d. -f2)" - targetfile="$name.$suffix" - [ $file != Makefile ] || targetfile=$file - cat $template/$file | sed -e 's/template/'$name'/' >$target/$targetfile -done - -exit 0 diff --git a/bit/src/m2764a/Makefile b/bit/src/m2764a/Makefile deleted file mode 100644 index 11e150d..0000000 --- a/bit/src/m2764a/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = m2764a -SRCS = $(NAME).v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/m2764a/m2764a.lso b/bit/src/m2764a/m2764a.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/m2764a/m2764a.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/m2764a/m2764a.prj b/bit/src/m2764a/m2764a.prj deleted file mode 100644 index 25e4d2c..0000000 --- a/bit/src/m2764a/m2764a.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "m2764a.v" diff --git a/bit/src/m2764a/m2764a.ucf b/bit/src/m2764a/m2764a.ucf deleted file mode 100644 index 17f86dc..0000000 --- a/bit/src/m2764a/m2764a.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/m2764a/m2764a.ut b/bit/src/m2764a/m2764a.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/m2764a/m2764a.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/m2764a/m2764a.v b/bit/src/m2764a/m2764a.v deleted file mode 100644 index 0082961..0000000 --- a/bit/src/m2764a/m2764a.v +++ /dev/null @@ -1,246 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * M2764A EPROM - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module m2764a(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 12MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - /* Programmer context */ - reg [1:0] prog_busy; - reg [3:0] prog_command; - reg [3:0] prog_state; - reg [7:0] prog_pulselen; - reg [7:0] prog_count; - `define PROG_PPULSE 1 - - /* DUT signals */ - reg [12:0] dut_addr; - reg [7:0] dut_data; - reg dut_E; - reg dut_P; - reg dut_G; - - assign low = 0; - assign high = 1; - - initial begin - prog_busy <= 0; - prog_command <= 0; - prog_state <= 0; - prog_pulselen <= 0; - prog_count <= 0; - dut_addr <= 0; - dut_data <= 0; - dut_E <= 1; - dut_P <= 1; - dut_G <= 1; - end - - /* The delay counter. Based on the 12MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - always @(posedge osc) begin - if (delay_count == 0) begin - if (prog_busy[0] != prog_busy[1]) begin - /* busy0 != busy1 indicates that a command is running. - * Continue executing it... */ - - case (prog_command) - `PROG_PPULSE: begin - case (prog_state) - 0: begin /* Init */ - dut_P <= 0; - prog_count <= prog_pulselen - 1; - prog_state <= 1; - delay_count <= 24000 - 2; - end - 1: begin /* Delay loop */ - if (prog_count == 0) begin - /* Done */ - dut_P <= 1; - prog_state <= 0; - prog_busy[1] <= prog_busy[0]; - end else begin - prog_state <= 2; - delay_count <= 24000 - 2; - end - end - 2: begin - prog_count <= prog_count - 1; - prog_state <= 1; - end - endcase - end - endcase - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - dut_data <= data; - end - 8'h12: begin - /* Run a command. */ - prog_command <= data; - prog_busy[0] <= ~prog_busy[1]; - end - 8'h13: begin - /* Set addr low */ - dut_addr[7:0] <= data; - end - 8'h14: begin - /* Set addr high */ - dut_addr[12:8] <= data[4:0]; - end - 8'h15: begin - /* Set P pulse len */ - prog_pulselen <= data; - end - 8'h16: begin - /* Set E/G */ - dut_E <= data[0]; - dut_G <= data[1]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - read_data[2:0] <= zif[23:21]; - read_data[7:3] <= zif[29:25]; - end - 8'h12: begin - /* Read status */ - read_data[0] <= (prog_busy[0] != prog_busy[1]); - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, high); /* VPP */ - bufif0(zif[12], dut_addr[12], low); /* A12 */ - bufif0(zif[13], dut_addr[7], low); /* A7 */ - bufif0(zif[14], dut_addr[6], low); /* A6 */ - bufif0(zif[15], dut_addr[5], low); /* A5 */ - bufif0(zif[16], dut_addr[4], low); /* A4 */ - bufif0(zif[17], dut_addr[3], low); /* A3 */ - bufif0(zif[18], dut_addr[2], low); /* A2 */ - bufif0(zif[19], dut_addr[1], low); /* A1 */ - bufif0(zif[20], dut_addr[0], low); /* A0 */ - bufif0(zif[21], dut_data[0], !dut_G); /* Q0 */ - bufif0(zif[22], dut_data[1], !dut_G); /* Q1 */ - bufif0(zif[23], dut_data[2], !dut_G); /* Q2 */ - bufif0(zif[24], low, low); /* Vss */ - bufif0(zif[25], dut_data[3], !dut_G); /* Q3 */ - bufif0(zif[26], dut_data[4], !dut_G); /* Q4 */ - bufif0(zif[27], dut_data[5], !dut_G); /* Q5 */ - bufif0(zif[28], dut_data[6], !dut_G); /* Q6 */ - bufif0(zif[29], dut_data[7], !dut_G); /* Q7 */ - bufif0(zif[30], dut_E, low); /* E */ - bufif0(zif[31], dut_addr[10], low); /* A10 */ - bufif0(zif[32], dut_G, low); /* G */ - bufif0(zif[33], dut_addr[11], low); /* A11 */ - bufif0(zif[34], dut_addr[9], low); /* A9 */ - bufif0(zif[35], dut_addr[8], low); /* A8 */ - bufif0(zif[36], low, low); /* NC */ - bufif0(zif[37], dut_P, low); /* P */ - bufif0(zif[38], high, low); /* Vcc */ - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/m2764a/m2764a.xst b/bit/src/m2764a/m2764a.xst deleted file mode 100644 index bf215df..0000000 --- a/bit/src/m2764a/m2764a.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn m2764a.prj --ifmt mixed --ofn m2764a --ofmt NGC --p xc2s15-5-vq100 --top m2764a --opt_mode Speed --opt_level 1 --iuc NO --lso m2764a.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/m8c-issp/Makefile b/bit/src/m8c-issp/Makefile deleted file mode 100644 index 96da03b..0000000 --- a/bit/src/m8c-issp/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = m8c-issp -SRCS = m8c-issp.v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/m8c-issp/m8c-issp.lso b/bit/src/m8c-issp/m8c-issp.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/m8c-issp/m8c-issp.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/m8c-issp/m8c-issp.prj b/bit/src/m8c-issp/m8c-issp.prj deleted file mode 100644 index 9394251..0000000 --- a/bit/src/m8c-issp/m8c-issp.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "m8c-issp.v" diff --git a/bit/src/m8c-issp/m8c-issp.ucf b/bit/src/m8c-issp/m8c-issp.ucf deleted file mode 100644 index 17f86dc..0000000 --- a/bit/src/m8c-issp/m8c-issp.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/m8c-issp/m8c-issp.ut b/bit/src/m8c-issp/m8c-issp.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/m8c-issp/m8c-issp.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/m8c-issp/m8c-issp.v b/bit/src/m8c-issp/m8c-issp.v deleted file mode 100644 index 7ed28fa..0000000 --- a/bit/src/m8c-issp/m8c-issp.v +++ /dev/null @@ -1,417 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Cypress M8C In System Serial Programmer - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module m8c_issp(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 12MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - /* The M8C programmer context */ - `define ISSP_VEC_SIZE 22 /* bits */ - reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */ - reg [7:0] issp_command; /* Currently loaded command */ - reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */ - reg [`ISSP_VEC_SIZE-1:0] issp_input_mask; /* Vector input bits mask */ - reg [`ISSP_VEC_SIZE-1:0] issp_input_vector; /* Read data */ - reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */ - reg [7:0] issp_count; /* General purpose counter */ - reg [3:0] issp_state; /* Statemachine */ - - /* The M8C programmer commands */ - `define ISSPCMD_NONE 0 /* No command loaded */ - `define ISSPCMD_POR 1 /* Perform a power-on-reset */ - `define ISSPCMD_PWROFF 2 /* Turn power off */ - `define ISSPCMD_SENDVEC 3 /* Send the vector */ - `define ISSPCMD_EXEC 4 /* Do an "execute" transfer */ - - /* The M8C device signals */ - reg dut_sdata; - reg dut_sdata_input; - reg dut_sclk; - reg dut_sclk_z; - reg dut_vdd; - `define VDD_ON 0 - `define VDD_OFF 1 - `define ZIF_SDATA 22 /* SDATA ZIF pin */ - - assign low = 0; - assign high = 1; - - initial begin - issp_busy <= 0; - issp_command <= 0; - issp_vector <= 0; - issp_vecbit <= `ISSP_VEC_SIZE; - issp_state <= 0; - dut_sdata <= 0; - dut_sdata_input <= 1; - dut_sclk <= 0; - dut_sclk_z <= 1; - dut_vdd <= `VDD_OFF; - read_data <= 0; - end - - /* The delay counter. Based on the 12MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - always @(posedge osc) begin - if (delay_count == 0) begin - if (issp_busy[0] != issp_busy[1]) begin - /* busy0 != busy1 indicates that a command is running. - * Continue executing it... */ - - if (issp_command == `ISSPCMD_POR) begin - case (issp_state) - 0: begin - /* Turn on power and wait vDDwait time */ - dut_vdd <= `VDD_ON; - dut_sclk_z <= 1; - dut_sclk <= 0; - dut_sdata_input <= 1; -// delay_count <= 24000 - 1; /* Wait 1ms */ - delay_count <= 12000 - 1; -// delay_count <= 5000 - 1; - issp_state <= 1; - end - 1: begin - if (zif[`ZIF_SDATA] == 1) begin - issp_state <= 2; - delay_count <= 6 - 1; /* Wait 250ns */ - end - end - 2: begin - if (zif[`ZIF_SDATA] == 0) begin - issp_state <= 3; - dut_sclk_z <= 0; - dut_sclk <= 0; - delay_count <= 6 - 1; /* Wait 250ns */ - end - end - 3: begin - if (issp_vecbit == 0) begin - dut_sdata_input <= 1; - issp_state <= 5; - end else begin - /* Ok, ready to send the next bit */ - dut_sclk_z <= 0; - dut_sdata_input <= 0; - dut_sdata <= issp_vector[issp_vecbit - 1]; - dut_sclk <= 1; - issp_state <= 4; - delay_count <= 6 - 1; /* Wait 250ns */ - end - end - 4: begin - dut_sclk <= 0; - issp_state <= 3; - issp_vecbit <= issp_vecbit - 1; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 5: begin - /* We're done. */ - issp_busy[1] <= issp_busy[0]; - issp_vecbit <= `ISSP_VEC_SIZE; - issp_state <= 0; - end - endcase - end - if (issp_command == `ISSPCMD_PWROFF) begin - dut_vdd <= `VDD_OFF; - dut_sdata_input <= 1; - dut_sclk_z <= 1; - /* We're done. */ - issp_busy[1] <= issp_busy[0]; - end - if (issp_command == `ISSPCMD_SENDVEC) begin - case (issp_state) - 0: begin - dut_sclk_z <= 0; - if (issp_input_mask[issp_vecbit - 1] == 0) begin - /* Send bit */ - dut_sdata_input <= 0; - dut_sdata <= issp_vector[issp_vecbit - 1]; - end - dut_sclk <= 1; - issp_state <= 1; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 1: begin - if (issp_input_mask[issp_vecbit - 1] != 0) begin - /* Receive bit */ - //FIXME? - dut_sdata_input <= 1; - issp_input_vector[issp_vecbit - 1] = zif[`ZIF_SDATA]; - end - dut_sclk <= 0; - issp_state <= 2; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 2: begin//FIXME? - if (issp_vecbit == 0) begin - /* We're done. */ - dut_sdata_input <= 1; - issp_busy[1] <= issp_busy[0]; - issp_vecbit <= `ISSP_VEC_SIZE; - issp_state <= 0; - end else begin - /* The next bit */ - issp_vecbit <= issp_vecbit - 1; - issp_state <= 0; - end - end - endcase - end - if (issp_command == `ISSPCMD_EXEC) begin - case (issp_state) - 0: begin /* Init */ - dut_sdata_input <= 1; - dut_sdata <= 0; - dut_sclk_z <= 0; - issp_count <= 40; - issp_state <= 1; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 1: begin /* Wait 40 cycles, set clk=hi */ - dut_sclk <= 1; - issp_state <= 2; - issp_count <= issp_count - 1; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 2: begin /* Wait 40 cycles, set clk=lo */ - dut_sclk <= 0; - if (issp_count == 0) - issp_state <= 3; - else - issp_state <= 1; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 3: begin /* Wait for SDATA=0, set clk=hi */ - dut_sclk <= 1; - dut_sdata_input <= 1; - dut_sdata <= 0; - if (zif[`ZIF_SDATA] == 0) begin - /* Ok, got it. Now send 40 zeros. */ - issp_count <= 39; - issp_state <= 5; - end else begin - issp_state <= 4; - end - delay_count <= 6 - 1; /* Wait 250ns */ - end - 4: begin /* Wait for SDATA=0, set clk=lo */ - dut_sclk <= 0; - issp_state <= 3; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 5: begin /* Send 40 zeros. set clk=lo */ - dut_sdata_input <= 0; - dut_sclk <= 0; - if (issp_count == 0) - issp_state <= 7; - else - issp_state <= 6; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 6: begin /* Send 40 zeros. set clk=hi */ - dut_sclk <= 1; - issp_count <= issp_count - 1; - issp_state <= 5; - delay_count <= 6 - 1; /* Wait 250ns */ - end - 7: begin /* finish */ - /* We're done. */ - issp_busy[1] <= issp_busy[0]; - dut_sdata_input <= 1; - issp_state <= 0; - end - endcase - end - end - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - /* Unused */ - end - 8'h12: begin - /* Load and execute command */ - issp_command <= data; - issp_busy[0] <= ~issp_busy[1]; - end - 8'h13: begin - /* Load vector low */ - issp_vector[7:0] <= data; - end - 8'h14: begin - /* Load vector med */ - issp_vector[15:8] <= data; - end - 8'h15: begin - /* Load vector high */ - issp_vector[21:16] <= data[5:0]; - end - 8'h16: begin - /* Load input mask low */ - issp_input_mask[7:0] <= data; - end - 8'h17: begin - /* Load input mask med */ - issp_input_mask[15:8] <= data; - end - 8'h18: begin - /* Load input mask high */ - issp_input_mask[21:16] <= data[5:0]; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - /* Unused */ - end - 8'h12: begin - /* Read status */ - read_data[0] <= (issp_busy[0] != issp_busy[1]); - end - 8'h13: begin - /* Read input vector low */ - read_data <= issp_input_vector[7:0]; - end - 8'h14: begin - /* Read input vector med */ - read_data <= issp_input_vector[15:8]; - end - 8'h15: begin - /* Read input vector high */ - read_data <= issp_input_vector[21:16]; - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - assign zif[20] = low; /* GND */ - assign zif[21] = high; /* VDD */ - bufif0(zif[`ZIF_SDATA], dut_sdata, dut_sdata_input); /* SDATA */ - bufif0(zif[23], dut_sclk, dut_sclk_z); /* SCLK */ - bufif0(zif[24], dut_vdd, low); /* VDDen */ - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], low, low); - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], low, low); - bufif0(zif[34], low, low); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/m8c-issp/m8c-issp.xst b/bit/src/m8c-issp/m8c-issp.xst deleted file mode 100644 index 6261e47..0000000 --- a/bit/src/m8c-issp/m8c-issp.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn m8c-issp.prj --ifmt mixed --ofn m8c-issp --ofmt NGC --p xc2s15-5-vq100 --top m8c_issp --opt_mode Speed --opt_level 1 --iuc NO --lso m8c-issp.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/template/Makefile b/bit/src/template/Makefile deleted file mode 100644 index 3f6d22f..0000000 --- a/bit/src/template/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = template -SRCS = $(NAME).v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/template/template.lso b/bit/src/template/template.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/template/template.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/template/template.prj b/bit/src/template/template.prj deleted file mode 100644 index 32dbdd2..0000000 --- a/bit/src/template/template.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "template.v" diff --git a/bit/src/template/template.ucf b/bit/src/template/template.ucf deleted file mode 100644 index 42bb7cc..0000000 --- a/bit/src/template/template.ucf +++ /dev/null @@ -1,62 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/template/template.ut b/bit/src/template/template.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/template/template.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/template/template.v b/bit/src/template/template.v deleted file mode 100644 index b25e086..0000000 --- a/bit/src/template/template.v +++ /dev/null @@ -1,158 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * XXXXXXXXXXXXXXXX - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module template(data, ale, write, read, osc_in, zif); - inout [7:0] data; - input ale; - input write; - input read; - input osc_in; /* 12MHz oscillator */ - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - wire low, high; /* Constant lo/hi */ - - assign low = 0; - assign high = 1; - - /* The delay counter. Based on the 12MHz input clock. */ - reg [15:0] delay_count; - wire osc; - IBUF osc_ibuf(.I(osc_in), .O(osc)); - - always @(posedge osc) begin - if (delay_count == 0) begin - - end else begin - delay_count <= delay_count - 1; - end - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - end - 8'h16: begin - /* Raw ZIF pin read access */ - read_data <= zif[8:1]; - end - 8'h17: begin - /* Raw ZIF pin read access */ - read_data <= zif[16:9]; - end - 8'h18: begin - /* Raw ZIF pin read access */ - read_data <= zif[24:17]; - end - 8'h19: begin - /* Raw ZIF pin read access */ - read_data <= zif[32:25]; - end - 8'h1A: begin - /* Raw ZIF pin read access */ - read_data <= zif[40:33]; - end - 8'h1B: begin - /* Raw ZIF pin read access */ - read_data <= zif[48:41]; - end - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif0(zif[1], low, low); - bufif0(zif[2], low, low); - bufif0(zif[3], low, low); - bufif0(zif[4], low, low); - bufif0(zif[5], low, low); - bufif0(zif[6], low, low); - bufif0(zif[7], low, low); - bufif0(zif[8], low, low); - bufif0(zif[9], low, low); - bufif0(zif[10], low, low); - bufif0(zif[11], low, low); - bufif0(zif[12], low, low); - bufif0(zif[13], low, low); - bufif0(zif[14], low, low); - bufif0(zif[15], low, low); - bufif0(zif[16], low, low); - bufif0(zif[17], low, low); - bufif0(zif[18], low, low); - bufif0(zif[19], low, low); - bufif0(zif[20], low, low); - bufif0(zif[21], low, low); - bufif0(zif[22], low, low); - bufif0(zif[23], low, low); - bufif0(zif[24], low, low); - bufif0(zif[25], low, low); - bufif0(zif[26], low, low); - bufif0(zif[27], low, low); - bufif0(zif[28], low, low); - bufif0(zif[29], low, low); - bufif0(zif[30], low, low); - bufif0(zif[31], low, low); - bufif0(zif[32], low, low); - bufif0(zif[33], low, low); - bufif0(zif[34], low, low); - bufif0(zif[35], low, low); - bufif0(zif[36], low, low); - bufif0(zif[37], low, low); - bufif0(zif[38], low, low); - bufif0(zif[39], low, low); - bufif0(zif[40], low, low); - bufif0(zif[41], low, low); - bufif0(zif[42], low, low); - bufif0(zif[43], low, low); - bufif0(zif[44], low, low); - bufif0(zif[45], low, low); - bufif0(zif[46], low, low); - bufif0(zif[47], low, low); - bufif0(zif[48], low, low); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/template/template.xst b/bit/src/template/template.xst deleted file mode 100644 index 00b1958..0000000 --- a/bit/src/template/template.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn template.prj --ifmt mixed --ofn template --ofmt NGC --p xc2s15-5-vq100 --top template --opt_mode Speed --opt_level 1 --iuc NO --lso template.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/src/unitest/Makefile b/bit/src/unitest/Makefile deleted file mode 100644 index 695029c..0000000 --- a/bit/src/unitest/Makefile +++ /dev/null @@ -1,37 +0,0 @@ -BITGEN = bitgen -PAR = par -MAP = map -NGDBUILD = ngdbuild -XST = xst -MKDIR = mkdir - -PART = 2s15vq100-5 -NAME = unitest -SRCS = $(NAME).v - -%.bit: %.ncd - $(BITGEN) -f `basename $< .ncd`.ut $< - -%.ncd: %_map.ncd - $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf - -%_map.ncd: %.ngd - $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf - -%.ngd: %.ngc - $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ - -%.ngc: %.xst $(SRCS) - $(MKDIR) -p __xst/tmp - $(XST) -ifn $< - -all: $(NAME).bit - -clean: - rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ - *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ - *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ - *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ - *.twr *_details.xml - - diff --git a/bit/src/unitest/unitest.lso b/bit/src/unitest/unitest.lso deleted file mode 100644 index b8f99f5..0000000 --- a/bit/src/unitest/unitest.lso +++ /dev/null @@ -1 +0,0 @@ -work diff --git a/bit/src/unitest/unitest.prj b/bit/src/unitest/unitest.prj deleted file mode 100644 index 6de4d45..0000000 --- a/bit/src/unitest/unitest.prj +++ /dev/null @@ -1 +0,0 @@ -verilog work "unitest.v" diff --git a/bit/src/unitest/unitest.ucf b/bit/src/unitest/unitest.ucf deleted file mode 100644 index f60e77e..0000000 --- a/bit/src/unitest/unitest.ucf +++ /dev/null @@ -1,65 +0,0 @@ -NET "data<0>" LOC = P30; -NET "data<1>" LOC = P31; -NET "data<2>" LOC = P32; -NET "data<3>" LOC = P34; -NET "data<4>" LOC = P40; -NET "data<5>" LOC = P41; -NET "data<6>" LOC = P43; -NET "data<7>" LOC = P44; - -NET "read" LOC = P45; -NET "write" LOC = P39; -#NET "osc_in" LOC = P46; -NET "ale" LOC = P36; - -#NET "txt" LOC = P52; #FIXME -#NET "rxt" LOC = P73; #FIXME - -NET "zif<1>" LOC = P21; -NET "zif<2>" LOC = P19; -NET "zif<3>" LOC = P17; -NET "zif<4>" LOC = P15; -NET "zif<5>" LOC = P10; -NET "zif<6>" LOC = P8; -NET "zif<7>" LOC = P6; -NET "zif<8>" LOC = P4; -NET "zif<9>" LOC = P98; -NET "zif<10>" LOC = P96; -NET "zif<11>" LOC = P93; -NET "zif<12>" LOC = P86; -NET "zif<13>" LOC = P83; -NET "zif<14>" LOC = P81; -NET "zif<15>" LOC = P74; -NET "zif<16>" LOC = P71; -NET "zif<17>" LOC = P69; -NET "zif<18>" LOC = P67; -NET "zif<19>" LOC = P65; -NET "zif<20>" LOC = P60; -NET "zif<21>" LOC = P58; -NET "zif<22>" LOC = P56; -NET "zif<23>" LOC = P54; -NET "zif<24>" LOC = P47; -NET "zif<25>" LOC = P53; -NET "zif<26>" LOC = P55; -NET "zif<27>" LOC = P57; -NET "zif<28>" LOC = P59; -NET "zif<29>" LOC = P62; -NET "zif<30>" LOC = P66; -NET "zif<31>" LOC = P68; -NET "zif<32>" LOC = P70; -NET "zif<33>" LOC = P72; -NET "zif<34>" LOC = P80; -NET "zif<35>" LOC = P82; -NET "zif<36>" LOC = P84; -NET "zif<37>" LOC = P87; -NET "zif<38>" LOC = P95; -NET "zif<39>" LOC = P97; -NET "zif<40>" LOC = P3; -NET "zif<41>" LOC = P5; -NET "zif<42>" LOC = P7; -NET "zif<43>" LOC = P9; -NET "zif<44>" LOC = P13; -NET "zif<45>" LOC = P16; -NET "zif<46>" LOC = P18; -NET "zif<47>" LOC = P20; -NET "zif<48>" LOC = P22; diff --git a/bit/src/unitest/unitest.ut b/bit/src/unitest/unitest.ut deleted file mode 100644 index 009a4e6..0000000 --- a/bit/src/unitest/unitest.ut +++ /dev/null @@ -1,29 +0,0 @@ --w --g DebugBitstream:No --g Binary:no --g Gclkdel0:11111 --g Gclkdel1:11111 --g Gclkdel2:11111 --g Gclkdel3:11111 --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullUp --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g StartUpClk:CClk --g DONE_cycle:4 --g GTS_cycle:5 --g GSR_cycle:6 --g GWE_cycle:6 --g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No diff --git a/bit/src/unitest/unitest.v b/bit/src/unitest/unitest.v deleted file mode 100644 index ee88bc8..0000000 --- a/bit/src/unitest/unitest.v +++ /dev/null @@ -1,180 +0,0 @@ -/* - * TOP2049 Open Source programming suite - * - * Universal device tester - * FPGA bottomhalf implementation - * - * Copyright (c) 2010 Michael Buesch - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -module unitest(data, ale, write, read, zif); - inout [7:0] data; - input ale; - input write; - input read; - inout [48:1] zif; - - /* Interface to the microcontroller */ - wire read_oe; /* Read output-enable */ - reg [7:0] address; /* Cached address value */ - reg [7:0] read_data; /* Cached read data */ - - /* ZIF pin controls */ - reg [47:0] zif_output_en; - reg [47:0] zif_output; - - initial begin - zif_output_en <= 0; - zif_output <= 0; - end - - always @(posedge write) begin - case (address) - 8'h10: begin - /* Data write */ - /* Unused */ - end - 8'h12: begin - zif_output_en[7:0] <= data; - end - 8'h13: begin - zif_output_en[15:8] <= data; - end - 8'h14: begin - zif_output_en[23:16] <= data; - end - 8'h15: begin - zif_output_en[31:24] <= data; - end - 8'h16: begin - zif_output_en[39:32] <= data; - end - 8'h17: begin - zif_output_en[47:40] <= data; - end - 8'h18: begin - zif_output[7:0] <= data; - end - 8'h19: begin - zif_output[15:8] <= data; - end - 8'h1A: begin - zif_output[23:16] <= data; - end - 8'h1B: begin - zif_output[31:24] <= data; - end - 8'h1C: begin - zif_output[39:32] <= data; - end - 8'h1D: begin - zif_output[47:40] <= data; - end - endcase - end - - always @(negedge read) begin - case (address) - 8'h10: begin - /* Data read */ - /* Unused */ - end - 8'h18: begin - read_data <= zif[8:1]; - end - 8'h19: begin - read_data <= zif[16:9]; - end - 8'h1A: begin - read_data <= zif[24:17]; - end - 8'h1B: begin - read_data <= zif[32:25]; - end - 8'h1C: begin - read_data <= zif[40:33]; - end - 8'h1D: begin - read_data <= zif[48:41]; - end - endcase - end - - always @(negedge ale) begin - address <= data; - end - - assign read_oe = !read && address[4]; - - bufif1(zif[1], zif_output[0], zif_output_en[0]); - bufif1(zif[2], zif_output[1], zif_output_en[1]); - bufif1(zif[3], zif_output[2], zif_output_en[2]); - bufif1(zif[4], zif_output[3], zif_output_en[3]); - bufif1(zif[5], zif_output[4], zif_output_en[4]); - bufif1(zif[6], zif_output[5], zif_output_en[5]); - bufif1(zif[7], zif_output[6], zif_output_en[6]); - bufif1(zif[8], zif_output[7], zif_output_en[7]); - bufif1(zif[9], zif_output[8], zif_output_en[8]); - bufif1(zif[10], zif_output[9], zif_output_en[9]); - bufif1(zif[11], zif_output[10], zif_output_en[10]); - bufif1(zif[12], zif_output[11], zif_output_en[11]); - bufif1(zif[13], zif_output[12], zif_output_en[12]); - bufif1(zif[14], zif_output[13], zif_output_en[13]); - bufif1(zif[15], zif_output[14], zif_output_en[14]); - bufif1(zif[16], zif_output[15], zif_output_en[15]); - bufif1(zif[17], zif_output[16], zif_output_en[16]); - bufif1(zif[18], zif_output[17], zif_output_en[17]); - bufif1(zif[19], zif_output[18], zif_output_en[18]); - bufif1(zif[20], zif_output[19], zif_output_en[19]); - bufif1(zif[21], zif_output[20], zif_output_en[20]); - bufif1(zif[22], zif_output[21], zif_output_en[21]); - bufif1(zif[23], zif_output[22], zif_output_en[22]); - bufif1(zif[24], zif_output[23], zif_output_en[23]); - bufif1(zif[25], zif_output[24], zif_output_en[24]); - bufif1(zif[26], zif_output[25], zif_output_en[25]); - bufif1(zif[27], zif_output[26], zif_output_en[26]); - bufif1(zif[28], zif_output[27], zif_output_en[27]); - bufif1(zif[29], zif_output[28], zif_output_en[28]); - bufif1(zif[30], zif_output[29], zif_output_en[29]); - bufif1(zif[31], zif_output[30], zif_output_en[30]); - bufif1(zif[32], zif_output[31], zif_output_en[31]); - bufif1(zif[33], zif_output[32], zif_output_en[32]); - bufif1(zif[34], zif_output[33], zif_output_en[33]); - bufif1(zif[35], zif_output[34], zif_output_en[34]); - bufif1(zif[36], zif_output[35], zif_output_en[35]); - bufif1(zif[37], zif_output[36], zif_output_en[36]); - bufif1(zif[38], zif_output[37], zif_output_en[37]); - bufif1(zif[39], zif_output[38], zif_output_en[38]); - bufif1(zif[40], zif_output[39], zif_output_en[39]); - bufif1(zif[41], zif_output[40], zif_output_en[40]); - bufif1(zif[42], zif_output[41], zif_output_en[41]); - bufif1(zif[43], zif_output[42], zif_output_en[42]); - bufif1(zif[44], zif_output[43], zif_output_en[43]); - bufif1(zif[45], zif_output[44], zif_output_en[44]); - bufif1(zif[46], zif_output[45], zif_output_en[45]); - bufif1(zif[47], zif_output[46], zif_output_en[46]); - bufif1(zif[48], zif_output[47], zif_output_en[47]); - - bufif1(data[0], read_data[0], read_oe); - bufif1(data[1], read_data[1], read_oe); - bufif1(data[2], read_data[2], read_oe); - bufif1(data[3], read_data[3], read_oe); - bufif1(data[4], read_data[4], read_oe); - bufif1(data[5], read_data[5], read_oe); - bufif1(data[6], read_data[6], read_oe); - bufif1(data[7], read_data[7], read_oe); -endmodule diff --git a/bit/src/unitest/unitest.xst b/bit/src/unitest/unitest.xst deleted file mode 100644 index 1fa414b..0000000 --- a/bit/src/unitest/unitest.xst +++ /dev/null @@ -1,57 +0,0 @@ -set -tmpdir __xst/tmp -set -xsthdpdir __xst -run --ifn unitest.prj --ifmt mixed --ofn unitest --ofmt NGC --p xc2s15-5-vq100 --top unitest --opt_mode Speed --opt_level 1 --iuc NO --lso unitest.lso --keep_hierarchy NO --rtlview Yes --glob_opt AllClockNets --read_cores YES --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 --verilog2001 YES --fsm_extract YES -fsm_encoding Auto --safe_implementation No --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract YES --shreg_extract YES --shift_extract YES --xor_collapse YES --rom_style Auto --auto_bram_packing NO --mux_extract YES --resource_sharing YES --async_to_sync NO --mult_style lut --iobuf YES --max_fanout 100 --bufg 4 --register_duplication YES --register_balancing No --slice_packing YES --optimize_primitives NO --tristate2logic Yes --use_clock_enable Yes --use_sync_set Yes --use_sync_reset Yes --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 diff --git a/bit/unitest.bit b/bit/unitest.bit deleted file mode 100644 index 376fc50..0000000 Binary files a/bit/unitest.bit and /dev/null differ diff --git a/bitfile.py b/bitfile.py deleted file mode 100644 index 69b09ef..0000000 --- a/bitfile.py +++ /dev/null @@ -1,162 +0,0 @@ -""" -# *.BIT file parser -# -# Copyright (c) 2009 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -import sys - -class BitfileException(Exception): pass - -class Bitfile: - # Magic header - MAGIC = "\x00\x09\x0f\xf0\x0f\xf0\x0f\xf0\x0f\xf0\x00\x00\x01" - # Field IDs - FIELD_SRCFILE = 0x61 - FIELD_FPGA = 0x62 - FIELD_DATE = 0x63 - FIELD_TIME = 0x64 - FIELD_PAYLOAD = 0x65 - - def __init__(self): - self.filename = "" - self.srcfile = "" - self.fpga = "" - self.date = "" - self.time = "" - self.payload = "" - - def getFilename(self): - return self.filename - - def getSrcFile(self): - return self.srcfile - - def getFPGA(self): - return self.fpga - - def getDate(self): - return self.date - - def getTime(self): - return self.time - - def getPayload(self): - return self.payload - - def parseFile(self, filename): - try: - data = file(filename, "rb").read() - except (IOError), e: - raise BitfileException("Failed to read \"" + filename + "\": " + e.strerror) - self.filename = filename - self.__parse(data) - - def __parse(self, data): - try: - magic = data[0:len(self.MAGIC)] - if magic != self.MAGIC: - raise BitfileException("Invalid magic header") - i = len(self.MAGIC) - while i < len(data): - i += self.__parseNextField(data, i) - except (IndexError), e: - raise BitfileException("Failed to parse BIT file") - if not self.fpga: - raise BitfileException("No FPGA ID string found") - if not self.payload: - raise BitfileException("No payload found") - - def __parseNextField(self, data, i): - fieldId = ord(data[i + 0]) - if (fieldId == self.FIELD_SRCFILE): - data = self.__parse16bitField(data, i + 1) - self.srcfile = data.strip().strip("\x00") - return len(data) + 3 - if (fieldId == self.FIELD_FPGA): - data = self.__parse16bitField(data, i + 1) - self.fpga = data.strip().strip("\x00") - return len(data) + 3 - if (fieldId == self.FIELD_DATE): - data = self.__parse16bitField(data, i + 1) - self.date = data.strip().strip("\x00") - return len(data) + 3 - if (fieldId == self.FIELD_TIME): - data = self.__parse16bitField(data, i + 1) - self.time = data.strip().strip("\x00") - return len(data) + 3 - if (fieldId == self.FIELD_PAYLOAD): - self.payload = self.__parse32bitField(data, i + 1) - return len(self.payload) + 5 - raise BitfileException("Found unknown data field 0x%02X" % fieldId) - - def __parse16bitField(self, data, i): - fieldLen = (ord(data[i + 0]) << 8) | ord(data[i + 1]) - return data[i + 2 : i + 2 + fieldLen] - - def __parse32bitField(self, data, i): - fieldLen = (ord(data[i + 0]) << 24) | (ord(data[i + 1]) << 16) |\ - (ord(data[i + 2]) << 8) | ord(data[i + 3]) - return data[i + 4 : i + 4 + fieldLen] - -def __probeFile(fullpath): - try: - file(fullpath, "rb") - except (IOError), e: - return False - return True - -def bitfileFind(filename): - "Search some standard paths for a bitfile" - if not filename.endswith(".bit"): - filename += ".bit" - if __probeFile(filename): - return filename - paths = ( ".", "./bit", "/usr/share/toprammer/bit", - "/usr/local/share/toprammer/bit", ) - for path in paths: - fullpath = path + "/" + filename - if __probeFile(fullpath): - return fullpath - return None - -if __name__ == "__main__": - if len(sys.argv) != 3: - print "Usage: %s file.bit ACTION" - print "" - print "Actions:" - print " GETSRC - print the src-file field to stdout" - print " GETFPGA - print the fpga-type field to stdout" - print " GETDATE - print the date field to stdout" - print " GETTIME - print the time field to stdout" - print " GETPAYLOAD - print the payload field to stdout" - sys.exit(1) - filename = sys.argv[1] - action = sys.argv[2].upper() - - b = Bitfile() - b.parseFile(filename) - if action == "GETSRC": - sys.stdout.write(b.getSrcFile()) - if action == "GETFPGA": - sys.stdout.write(b.getFPGA()) - if action == "GETDATE": - sys.stdout.write(b.getDate()) - if action == "GETTIME": - sys.stdout.write(b.getTime()) - if action == "GETPAYLOAD": - sys.stdout.write(b.getPayload()) diff --git a/chip.py b/chip.py deleted file mode 100644 index 876c948..0000000 --- a/chip.py +++ /dev/null @@ -1,149 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Chip support -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from util import * - - -supportedChips = [] - -class Chip: - def __init__(self, chipID, broken=False): - "The chipID is the ID string from the bitfile." - self.chipID = chipID - self.broken = broken - self.printPrefix = True - - def getID(self): - return self.chipID - - def isBroken(self): - return self.broken - - def setTOP(self, top): - self.top = top - - def printWarning(self, message, newline=True): - if self.printPrefix: - message = self.chipID + ": " + message - self.top.printWarning(message, newline) - self.printPrefix = newline - - def printInfo(self, message, newline=True): - if self.printPrefix: - message = self.chipID + ": " + message - self.top.printInfo(message, newline) - self.printPrefix = newline - - def printDebug(self, message, newline=True): - if self.printPrefix: - message = self.chipID + ": " + message - self.top.printDebug(message, newline) - self.printPrefix = newline - - def throwError(self, message): - raise TOPException(self.chipID + ": " + message) - - def progressMeterInit(self, message, nrSteps): - self.progressNrSteps = nrSteps - self.progressHave25 = False - self.progressHave50 = False - self.progressHave75 = False - self.printInfo(message + " [0%", newline=False) - - def progressMeterFinish(self): - if not self.progressNrSteps: - self.printInfo("...", newline=False) - self.printInfo("100%]") - - def progressMeter(self, step): - if step % (self.progressNrSteps // 32) == 0: - percent = (step * 100 // self.progressNrSteps) - if percent >= 25 and not self.progressHave25: - self.printInfo("25%", newline=False) - self.progressHave25 = True - elif percent >= 50 and not self.progressHave50: - self.printInfo("50%", newline=False) - self.progressHave50 = True - elif percent >= 75 and not self.progressHave75: - self.printInfo("75%", newline=False) - self.progressHave75 = True - else: - self.printInfo(".", newline=False) - - def initializeChip(self): - pass # Override me in the subclass, if required. - - def shutdownChip(self): - pass # Override me in the subclass, if required. - - def readSignature(self): - # Override me in the subclass, if required. - raise TOPException("Signature reading not supported on " + self.chipID) - - def erase(self): - # Override me in the subclass, if required. - raise TOPException("Chip erasing not supported on " + self.chipID) - - def readProgmem(self): - # Override me in the subclass, if required. - raise TOPException("Program memory reading not supported on " + self.chipID) - - def writeProgmem(self, image): - # Override me in the subclass, if required. - raise TOPException("Program memory writing not supported on " + self.chipID) - - def readEEPROM(self): - # Override me in the subclass, if required. - raise TOPException("EEPROM reading not supported on " + self.chipID) - - def writeEEPROM(self, image): - # Override me in the subclass, if required. - raise TOPException("EEPROM writing not supported on " + self.chipID) - - def readFuse(self): - # Override me in the subclass, if required. - raise TOPException("Fuse reading not supported on " + self.chipID) - - def writeFuse(self, image): - # Override me in the subclass, if required. - raise TOPException("Fuse writing not supported on " + self.chipID) - - def readLockbits(self): - # Override me in the subclass, if required. - raise TOPException("Lockbit reading not supported on " + self.chipID) - - def writeLockbits(self, image): - # Override me in the subclass, if required. - raise TOPException("Lockbit writing not supported on " + self.chipID) - -def chipFind(chipID): - for chip in supportedChips: - if chip.getID().lower() == chipID.lower(): - return chip - return None - -def dumpSupportedChips(fd): - for chip in supportedChips: - broken = "" - if chip.isBroken(): - broken = " (broken)" - fd.write("%20s%s\n" % (chip.getID(), broken)) diff --git a/chip_atmega32dip40.py b/chip_atmega32dip40.py deleted file mode 100644 index d82591f..0000000 --- a/chip_atmega32dip40.py +++ /dev/null @@ -1,41 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Atmel Mega32 DIP40 support -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip_atmega_common import * - -# Note: Chip has to be inserted upside-down into the ZIF - -class Chip_ATMega32DIP40(Chip_ATMega_common): - def __init__(self): - Chip_ATMega_common.__init__(self, - chipID = "atmega32dip40", - signature = "\x1E\x95\x02", - presenceCheckLayout = 0x0043FF000000, - GNDLayout = (35,), - VCCXLayout = (34,), - VPPLayout = (5, 6, 7, 9, 11, 12, 13, 14, 15, 16, 18, 19, 24, 26, 30, 31, 32, 33), - flashPageSize = 64, - flashPages = 256, - eepromPageSize = 4, - eepromPages = 256) - -supportedChips.append(Chip_ATMega32DIP40()) diff --git a/chip_atmega88dip28.py b/chip_atmega88dip28.py deleted file mode 100644 index baa498a..0000000 --- a/chip_atmega88dip28.py +++ /dev/null @@ -1,40 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Atmel Mega88 DIP28 support -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip_atmega_common import * - - -class Chip_ATMega88DIP28(Chip_ATMega_common): - def __init__(self): - Chip_ATMega_common.__init__(self, - chipID = "atmega88dip28", - signature = "\x1E\x93\x0A", - presenceCheckLayout = 0x00031F801000, - GNDLayout = (18,), - VCCXLayout = (17,), - VPPLayout = (5, 6, 7, 9, 11), - flashPageSize = 32, - flashPages = 128, - eepromPageSize = 4, - eepromPages = 128) - -supportedChips.append(Chip_ATMega88DIP28()) diff --git a/chip_atmega8dip28.py b/chip_atmega8dip28.py deleted file mode 100644 index d0fc660..0000000 --- a/chip_atmega8dip28.py +++ /dev/null @@ -1,40 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Atmel Mega8 DIP28 support -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip_atmega_common import * - - -class Chip_ATMega8DIP28(Chip_ATMega_common): - def __init__(self): - Chip_ATMega_common.__init__(self, - chipID = "atmega8dip28", - signature = "\x1E\x93\x07", - presenceCheckLayout = 0x00031F801000, - GNDLayout = (18,), - VCCXLayout = (17,), - VPPLayout = (5, 6, 7, 9, 11), - flashPageSize = 32, - flashPages = 128, - eepromPageSize = 4, - eepromPages = 128) - -supportedChips.append(Chip_ATMega8DIP28()) diff --git a/chip_atmega_common.py b/chip_atmega_common.py deleted file mode 100644 index 265cdaa..0000000 --- a/chip_atmega_common.py +++ /dev/null @@ -1,511 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Atmel Mega common support -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip import * - - -class Chip_ATMega_common(Chip): - # The Atmel Mega programming commands - CMD_CHIPERASE = 0x80 # Chip Erase - CMD_WRITEFUSE = 0x40 # Write Fuse Bits - CMD_WRITELOCK = 0x20 # Write Lock Bits - CMD_WRITEFLASH = 0x10 # Write Flash - CMD_WRITEEEPROM = 0x11 # Write EEPROM - CMD_READSIG = 0x08 # Read Signature bytes and Calibration byte - CMD_READFUSELOCK = 0x04 # Read Fuse and Lock bits - CMD_READFLASH = 0x02 # Read Flash - CMD_READEEPROM = 0x03 # Read EEPROM - - def __init__(self, chipID, signature, - presenceCheckLayout, - GNDLayout, VCCXLayout, VPPLayout, - flashPageSize, flashPages, - eepromPageSize, eepromPages, - ): - Chip.__init__(self, chipID) - self.signature = signature - self.presenceCheckLayout = presenceCheckLayout - self.GNDLayout = GNDLayout # List of GND ZIF pins - self.VCCXLayout = VCCXLayout # List of VCCX ZIF pins - self.VPPLayout = VPPLayout # List of VPP ZIF pins - self.flashPageSize = flashPageSize # Flash page size, in words - self.flashPages = flashPages # Nr of flash pages - self.eepromPageSize = eepromPageSize # EEPROM page size, in bytes - self.eepromPages = eepromPages # Nr of EEPROM pages - assert(eepromPageSize <= 64) - - def initializeChip(self): - self.printDebug("Initializing chip") - self.top.gnd.setLayoutPins(self.GNDLayout) - self.top.vccx.setLayoutPins( [] ) - self.top.vpp.setLayoutPins( [] ) - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(0) - self.top.cmdSetVPPVoltage(12) - - def shutdownChip(self): - self.printDebug("Shutdown chip") - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(5) - self.top.vccx.setLayoutPins( [] ) - self.top.vpp.setLayoutPins( [] ) - self.top.gnd.setLayoutPins( [] ) - - def readSignature(self): - self.__initPins() - - (signature, calibration) = self.__readSigAndCalib() - - return signature - - def erase(self): - self.__initPins() - - self.progressMeterInit("Erasing chip", 0) - self.__loadCommand(self.CMD_CHIPERASE) - self.__pulseWR() - self.__waitForRDY() - self.progressMeterFinish() - - def readProgmem(self): - self.__initPins() - - self.progressMeterInit("Reading Flash", self.flashPages) - image = "" - for page in range(0, self.flashPages): - self.progressMeter(page) - readWords = 0 - for word in range(0, self.flashPageSize): - self.__loadCommand(self.CMD_READFLASH) - self.__loadAddr((page * self.flashPageSize) + word) - self.__readWordToStatusReg() - readWords += 1 - if readWords >= 32: - image += self.top.cmdReadStatusReg() - readWords = 0 - if readWords: - data = self.top.cmdReadStatusReg() - image += data[0:readWords] - self.progressMeterFinish() - return image - - def writeProgmem(self, image): - flashBytes = self.flashPageSize * 2 * self.flashPages - if len(image) != flashBytes: - self.throwError("Invalid program memory image size %d (expected %d)" %\ - (len(image), flashBytes)) - self.__initPins() - - self.progressMeterInit("Writing Flash", self.flashPages) - for page in range(0, self.flashPages): - self.progressMeter(page) - for word in range(0, self.flashPageSize): - self.__loadCommand(self.CMD_WRITEFLASH) - addr = (page * self.flashPageSize) + word - self.__loadAddr(addr) - addr *= 2 - data = image[addr : addr + 2] - self.__loadData(ord(data[0]) | (ord(data[1]) << 8)) - self.__setBS1(1) - self.__pulsePAGEL() - self.__setBS1(0) - self.__pulseWR() - self.__waitForRDY() - self.progressMeterFinish() - - def readEEPROM(self): - self.__initPins() - - self.progressMeterInit("Reading EEPROM", self.eepromPages) - image = "" - for page in range(0, self.eepromPages): - self.progressMeter(page) - for byte in range(0, self.eepromPageSize): - self.__loadCommand(self.CMD_READEEPROM) - self.__loadAddr((page * self.eepromPageSize) + byte) - self.__readLowByteToStatusReg() - data = self.top.cmdReadStatusReg() - image += data[0:self.eepromPageSize] - self.progressMeterFinish() - return image - - def writeEEPROM(self, image): - eepromBytes = self.eepromPageSize * self.eepromPages - if len(image) != eepromBytes: - self.throwError("Invalid EEPROM image size %d (expected %d)" %\ - (len(image), eepromBytes)) - self.__initPins() - - self.progressMeterInit("Writing EEPROM", self.eepromPages) - for page in range(0, self.eepromPages): - self.progressMeter(page) - for byte in range(0, self.eepromPageSize): - self.__loadCommand(self.CMD_WRITEEEPROM) - addr = (page * self.eepromPageSize) + byte - self.__loadAddr(addr) - data = image[addr] - self.__loadDataLow(ord(data[0])) - self.__pulsePAGEL() - self.__setBS1(0) - self.__pulseWR() - self.__waitForRDY() - self.progressMeterFinish() - - def readFuse(self): - self.__initPins() - - self.progressMeterInit("Reading Fuse bits", 0) - (fuse, lock) = self.__readFuseAndLockBits() - self.progressMeterFinish() - return fuse - - def writeFuse(self, image): - if len(image) != 2: - self.throwError("Invalid Fuses image size %d (expected %d)" %\ - (len(image), 2)) - self.__initPins() - - self.progressMeterInit("Writing Fuse bits", 0) - self.__loadCommand(self.CMD_WRITEFUSE) - self.__setBS2(0) - self.__loadDataLow(ord(image[0])) - self.__pulseWR() - self.__waitForRDY() - self.__loadCommand(self.CMD_WRITEFUSE) - self.__loadDataLow(ord(image[1])) - self.__setBS1(1) - self.__pulseWR() - self.__waitForRDY() - self.progressMeterFinish() - - def readLockbits(self): - self.__initPins() - - self.progressMeterInit("Reading lock bits", 0) - (fuses, lockbits) = self.__readFuseAndLockBits() - self.progressMeterFinish() - - return lockbits - - def writeLockbits(self, image): - if len(image) != 1: - self.throwError("Invalid lock-bits image size %d (expected %d)" %\ - (len(image), 1)) - self.__initPins() - - self.progressMeterInit("Writing lock bits", 0) - self.__loadCommand(self.CMD_WRITELOCK) - self.__loadDataLow(ord(image[0])) - self.__pulseWR() - self.__waitForRDY() - self.progressMeterFinish() - - def __readSigAndCalib(self): - """Reads the signature and calibration bytes and returns them. - This function expects a DUT present and pins initialized.""" - signature = "" - calibration = "" - for addr in range(0, 4): - self.__loadCommand(self.CMD_READSIG) - self.__loadAddr(addr) - self.__readWordToStatusReg() - data = self.top.cmdReadStatusReg() - if addr <= 2: - signature += data[0] - calibration += data[1] - return (signature, calibration) - - def __readFuseAndLockBits(self): - """Reads the Fuse and Lock bits and returns them. - This function expects a DUT present and pins initialized.""" - self.__loadCommand(self.CMD_READFUSELOCK) - self.__setBS2(0) - self.__readWordToStatusReg() - self.__setBS2(1) - self.__readWordToStatusReg() - self.__setBS2(0) - data = self.top.cmdReadStatusReg() - fuses = data[0] + data[3] - lock = data[1] - return (fuses, lock) - - def __initPins(self): - """Initialize the pin voltages and logic.""" - self.top.vpp.setLayoutPins( [] ) - self.top.vccx.setLayoutPins( [] ) - self.top.queueCommand("\x0E\x28\x01\x00") - self.top.cmdFPGAWrite(0x1B, 0x00) - self.top.cmdSetVPPVoltage(0) - self.top.cmdSetVPPVoltage(12) - self.top.gnd.setLayoutPins(self.GNDLayout) - self.top.cmdSetVCCXVoltage(4.4) - - self.__setXA0(0) - self.__setXA1(0) - self.__setBS1(0) - self.__setWR(0) - self.top.flushCommands() - - self.top.gnd.setLayoutPins(self.GNDLayout) - self.top.vccx.setLayoutPins(self.VCCXLayout) - - self.top.cmdFPGAReadRaw(0x16) - self.top.cmdFPGAReadRaw(0x17) - self.top.cmdFPGAReadRaw(0x18) - self.top.cmdFPGAReadRaw(0x19) - self.top.cmdFPGAReadRaw(0x1A) - self.top.cmdFPGAReadRaw(0x1B) - stat = self.top.cmdReadStatusReg48() - if stat != self.presenceCheckLayout: - msg = "Did not detect chip. Please check connections. (0x%012X)" % stat - if self.top.getForceLevel() >= 2: - self.printWarning(msg) - else: - self.throwError(msg) - - self.top.queueCommand("\x19") - self.__setReadMode(0) - self.top.queueCommand("\x34") - self.__setReadMode(0) - self.__setOE(0) - self.__setWR(1) - self.__setXTAL1(0) - self.__setXA0(0) - self.__setXA1(0) - self.top.cmdFPGAWrite(0x12, 0x08) - self.__setBS1(0) - self.__setBS2(0) - self.__setPAGEL(0) - self.__pulseXTAL1(10) - self.top.queueCommand("\x19") - self.top.flushCommands() - - self.top.vpp.setLayoutPins(self.VPPLayout) - - self.top.queueCommand("\x34") - self.top.cmdFPGAWrite(0x12, 0x88) - self.__setOE(1) - self.top.cmdFlush() - - (signature, calibration) = self.__readSigAndCalib() - if signature != self.signature: - msg = "Unexpected device signature. " +\ - "Want %02X%02X%02X, but got %02X%02X%02X" % \ - (ord(self.signature[0]), ord(self.signature[1]), - ord(self.signature[2]), - ord(signature[0]), ord(signature[1]), - ord(signature[2])) - if self.top.getForceLevel() >= 1: - self.printWarning(msg) - else: - self.throwError(msg) - - self.top.cmdFlush(10) - self.top.queueCommand("\x0E\x1F\x00\x00") - self.top.delay(0.1) - stat = self.top.cmdReadStatusReg32() - if stat != 0xB9C80101: - self.throwError("read: Unexpected status value 0x%08X" % stat) - - def __readWordToStatusReg(self): - """Read a data word from the DUT into the status register.""" - self.__setReadMode(1) - self.__setBS1(0) - self.__setOE(0) - self.top.cmdFPGAReadByte() - self.__setBS1(1) - self.top.cmdFPGAReadByte() - self.__setOE(1) - self.__setReadMode(0) - - def __readLowByteToStatusReg(self): - """Read the low data byte from the DUT into the status register.""" - self.__setReadMode(1) - self.__setBS1(0) - self.__setOE(0) - self.top.cmdFPGAReadByte() - self.__setOE(1) - self.__setReadMode(0) - - def __readHighByteToStatusReg(self): - """Read the high data byte from the DUT into the status register.""" - self.__setReadMode(1) - self.__setBS1(1) - self.__setOE(0) - self.top.cmdFPGAReadByte() - self.__setOE(1) - self.__setReadMode(0) - - def __loadData(self, data): - """Load a data word.""" - self.__loadDataLow(data) - self.__loadDataHigh(data >> 8) - - def __loadDataLow(self, dataLow): - """Load the low data byte.""" - self.__setBS1(0) - self.__setXA0(1) - self.__setXA1(0) - self.top.cmdFPGAWrite(0x10, dataLow & 0xFF) - self.__pulseXTAL1() - - def __loadDataHigh(self, dataHigh): - """Load the high data byte.""" - self.__setBS1(1) - self.__setXA0(1) - self.__setXA1(0) - self.top.cmdFPGAWrite(0x10, dataHigh & 0xFF) - self.__pulseXTAL1() - - def __loadAddr(self, addr): - """Load an address word.""" - self.__loadAddrLow(addr) - self.__loadAddrHigh(addr >> 8) - - def __loadAddrLow(self, addrLow): - """Load the low address byte.""" - self.__setBS1(0) - self.__setXA0(0) - self.__setXA1(0) - self.top.cmdFPGAWrite(0x10, addrLow & 0xFF) - self.__pulseXTAL1() - - def __loadAddrHigh(self, addrHigh): - """Load the high address byte.""" - self.__setBS1(1) - self.__setXA0(0) - self.__setXA1(0) - self.top.cmdFPGAWrite(0x10, addrHigh & 0xFF) - self.__pulseXTAL1() - - def __loadCommand(self, command): - """Load a command into the device.""" - self.top.queueCommand("\x34") - self.__setBS1(0) - self.top.queueCommand("\x34") - self.__setXA0(0) - self.__setXA1(1) - self.top.cmdFPGAWrite(0x10, command) - self.__pulseXTAL1() - - def __setReadMode(self, high): - """Put the FPGA into read mode.""" - value = 0x01 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __waitForRDY(self): - """Wait for the RDY pin to go high.""" - self.top.delay(0.01) - for i in range(0, 50): - if self.__getRDY(): - return - self.top.delay(0.01) - self.throwError("Timeout waiting for READY signal from chip.") - - def __getRDY(self): - """Read the state of the RDY/BSY pin.""" - return bool(self.__getStatus() & 0x01) - - def __getStatus(self): - """Read the programmer status register""" - self.top.cmdFPGAReadRaw(0x12) - stat = self.top.cmdReadStatusReg() - return ord(stat[0]) - - def __setOE(self, high): - """Set the OE pin of the DUT""" - value = 0x02 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __setWR(self, high): - """Set the WR pin of the DUT""" - value = 0x03 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __pulseWR(self, count=1): - """Do a negative pulse on the WR pin of the DUT""" - while count > 0: - self.__setWR(0) - self.__setWR(1) - count -= 1 - - def __setBS1(self, high): - """Set the BS1 pin of the DUT""" - value = 0x04 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __setXA0(self, high): - """Set the XA0 pin of the DUT""" - value = 0x05 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __setXA1(self, high): - """Set the XA1 pin of the DUT""" - value = 0x06 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __setXTAL1(self, high): - """Set the XTAL1 pin of the DUT""" - value = 0x07 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __pulseXTAL1(self, count=1): - """Do a positive pulse on the XTAL1 pin of the DUT""" - while count > 0: - self.__setXTAL1(1) - self.__setXTAL1(0) - count -= 1 - - def __setPAGEL(self, high): - """Set the PAGEL pin of the DUT""" - value = 0x09 - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) - - def __pulsePAGEL(self, count=1): - """Do a positive pulse on the PAGEL pin of the DUT""" - while count > 0: - self.__setPAGEL(1) - self.__setPAGEL(0) - count -= 1 - - def __setBS2(self, high): - """Set the BS2 pin of the DUT""" - value = 0x0A - if high: - value |= 0x80 - self.top.cmdFPGAWrite(0x12, value) diff --git a/chip_m2764a.py b/chip_m2764a.py deleted file mode 100644 index ca1aff9..0000000 --- a/chip_m2764a.py +++ /dev/null @@ -1,161 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# M2764A EPROM programmer -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip import * - - -class M2764A(Chip): - PROGCMD_PPULSE = 1 # Perform a P-pulse - - STAT_BUSY = 0x01 # Programmer is running a command - - def __init__(self): - Chip.__init__(self, "m2764a", broken=True) - - def initializeChip(self): - self.printDebug("Initializing chip") - self.top.vccx.setLayoutMask(0) - self.top.vpp.setLayoutMask(0) - self.top.gnd.setLayoutPins( [] ) - self.top.queueCommand("\x0E\x28\x01\x00") - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(0) - self.top.cmdSetVPPVoltage(5) - - def shutdownChip(self): - self.printDebug("Shutdown chip") - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(5) - self.top.vccx.setLayoutMask(0) - self.top.vpp.setLayoutMask(0) - self.top.gnd.setLayoutPins( [] ) - - def readEEPROM(self): - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(5) - self.top.vccx.setLayoutPins( (38,) ) - self.top.vpp.setLayoutPins( (5, 6, 7, 9, 11) ) - self.top.gnd.setLayoutPins( (24,) ) - - image = "" - self.progressMeterInit("Reading EPROM", 0x2000) - self.__setEG(E=1, G=1) - for addr in range(0, 0x2000): - self.progressMeter(addr) - image += self.__readData(addr) - self.__setEG(E=1, G=1) - self.progressMeterFinish() - - return image - - def writeEEPROM(self, image): - if len(image) != 0x2000: - self.throwError("Invalid EPROM image size %d (expected %d)" %\ - (len(image), 0x2000)) - - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(12) - self.top.vccx.setLayoutPins( (38,) ) - self.top.vpp.setLayoutPins( (5, 6, 7, 9, 11) ) - self.top.gnd.setLayoutPins( (24,) ) - - self.progressMeterInit("Writing EPROM", 0x2000) - self.__setEG(E=1, G=1) - for addr in range(0, 0x2000): - self.progressMeter(addr) - self.__writeData(addr, ord(image[addr])) - self.__setEG(E=1, G=1) - self.progressMeterFinish() - - def __readData(self, addr): - self.__loadAddr(addr) - self.__setEG(E=0, G=0) - self.top.cmdFPGAReadByte() - stat = self.top.cmdReadStatusReg() - return stat[0] - - def __writeData(self, addr, data): - self.__setEG(E=0, G=1) - self.__loadAddr(addr) - self.__loadData(data) - self.__loadPPulseLen(1) - self.__runCommandSync(self.PROGCMD_PPULSE) - for i in range(0, 25): - r = ord(self.__readData(addr)) - if r == data: - break - self.__setEG(E=0, G=1) - self.__runCommandSync(self.PROGCMD_PPULSE) - else: - self.throwError("Failed to program 0x%04X (got 0x%02X, expected 0x%02X)" %\ - (addr, r, data)) - self.__setEG(E=0, G=1) - self.__loadPPulseLen(3 * (i + 1)) - self.__runCommandSync(self.PROGCMD_PPULSE) - - def __loadData(self, data): - self.top.cmdFPGAWrite(0x10, data) - - def __loadCommand(self, command): - self.top.cmdFPGAWrite(0x12, command & 0xFF) - - def __runCommandSync(self, command): - self.__loadCommand(command) - self.__busyWait() - - def __loadAddrLow(self, addrLow): - self.top.cmdFPGAWrite(0x13, addrLow & 0xFF) - - def __loadAddrHigh(self, addrHigh): - self.top.cmdFPGAWrite(0x14, addrHigh & 0xFF) - - def __loadAddr(self, addr): - self.__loadAddrLow(addr) - self.__loadAddrHigh(addr >> 8) - - def __loadPPulseLen(self, msec): - self.top.cmdFPGAWrite(0x15, msec) - - def __setEG(self, E, G): - data = 0 - if E: - data |= 1 - if G: - data |= 2 - self.top.cmdFPGAWrite(0x16, data) - - def __getStatusFlags(self): - self.top.cmdFPGAReadRaw(0x12) - stat = self.top.cmdReadStatusReg() - return ord(stat[0]) - - def __busy(self): - return bool(self.__getStatusFlags() & self.STAT_BUSY) - - def __busyWait(self): - for i in range(0, 100): - if not self.__busy(): - return - self.top.delay(0.01) - self.throwError("Timeout in busywait.") - -supportedChips.append(M2764A()) diff --git a/chip_m8cissp.py b/chip_m8cissp.py deleted file mode 100644 index 3f23a54..0000000 --- a/chip_m8cissp.py +++ /dev/null @@ -1,347 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Cypress M8C In System Serial Programmer -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip import * -import time - - -class M8C_ISSP(Chip): - ISSPCMD_POR = 1 # Perform a power-on-reset - ISSPCMD_PWROFF = 2 # Turn power off - ISSPCMD_SENDVEC = 3 # Send a vector - ISSPCMD_EXEC = 4 # Do an "execute" transfer - - STAT_BUSY = 0x01 # Programmer is running a command - - STRVEC_SETFREQ = { - 2 : "1001111110000000101000", - 3 : "1001111110000001001000", - 3.578 : "1001111110000001011000", - 4 : "1001111110000001101000", - 5 : "1001111110000010001000", - 6 : "1001111110000010101000", - 6.66666 : "1001111110000010111000", - 7 : "1001111110000011001000", - 8 : "1001111110000011100000", - 9 : "1001111110000100000000", - 10 : "1001111110000100100000", - 11 : "1001111110000101000000", - 12 : "1001111110000101100000", - } - STRVEC_INIT1 = ( - "1100101000000000000000", - "0000000000000000000000", - "0000000000000000000000", - "1000111101100100000000", - "1101111011100000000000", - "1101111011000001000000", - "1001111100000111010000", - "1001111100100001011000", - "1101111010100000000000", - "1101111010000000011000", - "1001111101100100000000", - "1101111100100110000000", - "1101111101001000000000", - "1101111000000001000000", - "1101111100000000000000", - "1101111111100010010000", - ) - STRVEC_INIT2 = ( - "1101111011100000000000", - "1101111011000001000000", - "1001111100000111010000", - "1001111100100001011000", - "1101111010100000000000", - "1101111010000000011000", - "1001111101100100000000", - "1101111100100110000000", - "1101111101001000000000", - "1001111101000000001000", - "1101111000000000110000", - "1101111100000000000000", - "1101111111100010010000", - ) - STRVEC_INIT3_HIVDD = ( - "1101111011100000000000", - "1101111010000000011000", - "1101111010100000000000", - "1101111011000001000000", - "1101111100001010001000", - "1101111100111111100000", - "1101111101000110000000", - "1101111111100010010000", - "0000000000000000000000", - "1101111011100000000000", - "1101111010000000011000", - "1101111010100000000000", - "1101111011000001000000", - "1101111100001100000000", - "1101111100111101010000", - "1101111101000110000000", - "1101111011100010000000", - "1101111111100010010000", - "0000000000000000000000", - ) - STRVEC_INIT3_LOVDD = ( - "1101111011100000000000", - "1101111010000000011000", - "1101111010100000000000", - "1101111011000001000000", - "1101111100001010001000", - "1101111100111111000000", - "1101111101000110000000", - "1101111111100010010000", - "0000000000000000000000", - "1101111011100000000000", - "1101111010000000011000", - "1101111010100000000000", - "1101111011000001000000", - "1101111100001100000000", - "1101111100111101010000", - "1101111101000110000000", - "1101111011100010000000", - "1101111111100010010000", - "0000000000000000000000", - ) - STRVEC_IDSETUP = ( - "1101111011100000000000", - "1101111011000001000000", - "1001111100000111010000", - "1001111100100001011000", - "1101111010100000000000", - "1101111010000000011000", - "1001111101100100000000", - "1101111100100110000000", - "1101111101001000000000", - "1001111101000000000000", - "1101111000000000110000", - "1101111100000000000000", - "1101111111100010010000", - ) - STRVEC_READBYTE = "101aaaaaaaaZDDDDDDDDZ0" - STRVEC_ERASEALL = ( - "1101111011100000000000", - "1101111011001000000000", - "1001111100000111010000", - "1001111100101000011000", - "1101111010100000000000", - "1101111010000000011000", - "1001111101110000000000", - "1101111100100110000000", - "1101111101001000000000", - "1101111000000000101000", - "1101111100000000000000", - "1101111111100010010000", - ) - STRVEC_SECURE = ( - "1101111011100000000000", - "1101111011001000000000", - "1001111100000111010000", - "1001111100101000011000", - "1101111010100000000000", - "1101111010000000011000", - "1001111101110000000000", - "1101111100100110000000", - "1101111101001000000000", - "1101111000000000100000", - "1101111100000000000000", - "1101111111100010010000", - ) - - def __init__(self): - Chip.__init__(self, "m8c-issp", broken=True) - - def initializeChip(self): - self.printDebug("Initializing chip") - self.top.vccx.setLayoutMask(0) - self.top.vpp.setLayoutMask(0) - self.top.gnd.setLayoutPins( [] ) - self.top.cmdSetVCCXVoltage(5) - self.top.cmdFlush() - self.top.cmdSetVPPVoltage(0) - self.top.cmdFlush() - self.top.cmdSetVPPVoltage(5) - - #XXX - self.__powerOnReset() - id = self.__readID() - print "ID=0x%04X" % id - - def shutdownChip(self): - self.printDebug("Shutdown chip") - self.top.cmdSetVCCXVoltage(5) - self.top.cmdFlush() - self.top.cmdSetVPPVoltage(5) - self.top.cmdFlush() - self.top.vccx.setLayoutMask(0) - self.top.vpp.setLayoutMask(0) - self.top.cmdFlush() - self.top.gnd.setLayoutPins( [] ) - - def __powerDown(self): - "Turn the power to the device off" - self.printDebug("Powering device down...") - self.__runCommandSync(self.ISSPCMD_PWROFF) - self.top.flushCommands() - time.sleep(3) - - def __powerOnReset(self): - "Perform a complete power-on-reset and initialization" - self.printDebug("Initializing supply power...") - self.top.gnd.setLayoutPins( (20,) ) - self.top.cmdFlush() - self.top.vccx.setLayoutPins( (21,) ) - self.top.cmdFlush() - self.top.cmdSetVCCXVoltage(5) - self.top.cmdFlush() - - self.__powerDown() - self.printDebug("Performing a power-on-reset...") - self.__loadStringVector(self.STRVEC_INIT1[0]) - self.__runCommandSync(self.ISSPCMD_POR) - self.printDebug("Sending vector 1...") - for vec in self.STRVEC_INIT1[1:]: - self.__loadStringVector(vec) - self.__runCommandSync(self.ISSPCMD_SENDVEC) - self.printDebug("Executing...") - self.__runCommandSync(self.ISSPCMD_EXEC) - self.printDebug("Sending vector 2...") - for vec in self.STRVEC_INIT2: - self.__loadStringVector(vec) - self.__runCommandSync(self.ISSPCMD_SENDVEC) - self.printDebug("Executing...") - self.__runCommandSync(self.ISSPCMD_EXEC) - self.printDebug("Sending vector 3...") - for vec in self.STRVEC_INIT3_HIVDD: - self.__loadStringVector(vec) - self.__runCommandSync(self.ISSPCMD_SENDVEC) - - def __readID(self): - "Read the silicon ID" - for vec in self.STRVEC_IDSETUP: - self.__loadStringVector(vec) - self.__runCommandSync(self.ISSPCMD_SENDVEC) - self.__runCommandSync(self.ISSPCMD_EXEC) - - low = self.__readByte(0xF8) - high = self.__readByte(0xF9) - - return low | (high << 8) - - def __readByte(self, address): - strVec = self.__stringVectorReplace(self.STRVEC_READBYTE, "a", address) - self.__loadStringVector(strVec) - self.__runCommandSync(self.ISSPCMD_SENDVEC) - input = self.__getInputVector() - return (input >> 2) & 0xFF - - def __loadCommand(self, command): - self.top.cmdFPGAWrite(0x12, command & 0xFF) - - def __runCommandSync(self, command): - self.__loadCommand(command) - self.__busyWait() - - def __loadVectorLow(self, vecLow): - self.top.cmdFPGAWrite(0x13, vecLow & 0xFF) - - def __loadVectorMed(self, vecMed): - self.top.cmdFPGAWrite(0x14, vecMed & 0xFF) - - def __loadVectorHigh(self, vecHigh): - self.top.cmdFPGAWrite(0x15, vecHigh & 0xFF) - - def __loadVector(self, vec): - self.__loadVectorLow(vec) - self.__loadVectorMed(vec >> 8) - self.__loadVectorHigh(vec >> 16) - - def __loadVectorInputMaskLow(self, maskLow): - self.top.cmdFPGAWrite(0x16, maskLow & 0xFF) - - def __loadVectorInputMaskMed(self, maskMed): - self.top.cmdFPGAWrite(0x17, maskMed & 0xFF) - - def __loadVectorInputMaskHigh(self, maskHigh): - self.top.cmdFPGAWrite(0x18, maskHigh & 0xFF) - - def __loadVectorInputMask(self, mask): - self.__loadVectorInputMaskLow(mask) - self.__loadVectorInputMaskMed(mask >> 8) - self.__loadVectorInputMaskHigh(mask >> 16) - - def __getStatusFlags(self): - self.top.cmdFPGAReadRaw(0x12) - stat = self.top.cmdReadStatusReg() - return ord(stat[0]) - - def __busy(self): - return bool(self.__getStatusFlags() & self.STAT_BUSY) - - def __busyWait(self): -#XXX for i in range(0, 50): - while 1: - if not self.__busy(): - return - time.sleep(0.01) - self.throwError("Timeout in busywait. Chip not responding?") - - def __getInputVector(self): - self.top.cmdFPGAReadRaw(0x13) - self.top.cmdFPGAReadRaw(0x14) - self.top.cmdFPGAReadRaw(0x15) - stat = self.top.cmdReadStatusReg() - return ord(stat[0]) | (ord(stat[1]) << 8) | (ord(stat[2]) << 16) - - def __stringVectorToBinary(self, vector): - binary = 0 - input = 0 - assert(len(vector) == 22) - bit = len(vector) - 1 - for b in vector: - if b == "1": - binary |= (1 << bit) - if b == "H" or b == "L" or b == "Z" or b == "D": - input |= (1 << bit) - bit -= 1 - return (binary, input) - - def __stringVectorReplace(self, strVec, replace, data): - ret = "" - for i in range(len(strVec) - 1, -1, -1): - b = strVec[i] - if b == replace: - if (data & 1): - ret = "1" + ret - else: - ret = "0" + ret - data >>= 1 - else: - ret = b + ret - return ret - - def __loadStringVector(self, strVec): - (vector, inputMask) = self.__stringVectorToBinary(strVec) - self.__loadVectorInputMask(inputMask) - self.__loadVector(vector) - -supportedChips.append(M8C_ISSP()) diff --git a/chip_unitest.py b/chip_unitest.py deleted file mode 100644 index a5d65ae..0000000 --- a/chip_unitest.py +++ /dev/null @@ -1,93 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Universal device tester -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from chip import * - - -class Chip_Unitest(Chip): - def __init__(self): - Chip.__init__(self, "unitest") - - def initializeChip(self): - self.printDebug("Initializing chip") - self.__reset() - - def shutdownChip(self): - self.printDebug("Shutdown chip") - self.__reset() - - def __reset(self): - self.top.vccx.setLayoutPins( [] ) - self.top.vpp.setLayoutPins( [] ) - self.top.gnd.setLayoutPins( [] ) - self.top.cmdSetVCCXVoltage(5) - self.top.cmdSetVPPVoltage(0) - self.top.cmdSetVPPVoltage(5) - self.setOutputEnableMask(0) - self.setOutputs(0) - - def setVCCX(self, voltage, layout): - self.top.cmdSetVCCXVoltage(0) - self.top.cmdLoadVCCXLayout(layout) - self.top.cmdSetVCCXVoltage(voltage) - self.top.flushCommands() - - def setVPP(self, voltage, layout): - self.top.cmdSetVPPVoltage(0) - self.top.cmdLoadVPPLayout(layout) - self.top.cmdSetVPPVoltage(voltage) - self.top.flushCommands() - #TODO: Disable outen on these pins - - def setGND(self, pin): - self.top.cmdSetGNDPin(pin) - self.top.flushCommands() - - def setOutputEnableMask(self, mask): - self.top.cmdFPGAWrite(0x12, mask & 0xFF) - self.top.cmdFPGAWrite(0x13, (mask >> 8) & 0xFF) - self.top.cmdFPGAWrite(0x14, (mask >> 16) & 0xFF) - self.top.cmdFPGAWrite(0x15, (mask >> 24) & 0xFF) - self.top.cmdFPGAWrite(0x16, (mask >> 32) & 0xFF) - self.top.cmdFPGAWrite(0x17, (mask >> 40) & 0xFF) - self.top.flushCommands() - - def setOutputs(self, mask): - self.top.cmdFPGAWrite(0x18, mask & 0xFF) - self.top.cmdFPGAWrite(0x19, (mask >> 8) & 0xFF) - self.top.cmdFPGAWrite(0x1A, (mask >> 16) & 0xFF) - self.top.cmdFPGAWrite(0x1B, (mask >> 24) & 0xFF) - self.top.cmdFPGAWrite(0x1C, (mask >> 32) & 0xFF) - self.top.cmdFPGAWrite(0x1D, (mask >> 40) & 0xFF) - self.top.flushCommands() - - def getInputs(self): - self.top.cmdFPGAReadRaw(0x18) - self.top.cmdFPGAReadRaw(0x19) - self.top.cmdFPGAReadRaw(0x1A) - self.top.cmdFPGAReadRaw(0x1B) - self.top.cmdFPGAReadRaw(0x1C) - self.top.cmdFPGAReadRaw(0x1D) - inputs = self.top.cmdReadStatusReg48() - return inputs - -supportedChips.append(Chip_Unitest()) diff --git a/libtoprammer/__init__.py b/libtoprammer/__init__.py new file mode 100644 index 0000000..8d1c8b6 --- /dev/null +++ b/libtoprammer/__init__.py @@ -0,0 +1 @@ + diff --git a/libtoprammer/bit/.gitignore b/libtoprammer/bit/.gitignore new file mode 100644 index 0000000..f9930d5 --- /dev/null +++ b/libtoprammer/bit/.gitignore @@ -0,0 +1 @@ +*.build.log diff --git a/libtoprammer/bit/atmega32dip40.bit b/libtoprammer/bit/atmega32dip40.bit new file mode 100644 index 0000000..d7a163d Binary files /dev/null and b/libtoprammer/bit/atmega32dip40.bit differ diff --git a/libtoprammer/bit/atmega88dip28.bit b/libtoprammer/bit/atmega88dip28.bit new file mode 100644 index 0000000..02f0964 Binary files /dev/null and b/libtoprammer/bit/atmega88dip28.bit differ diff --git a/libtoprammer/bit/atmega8dip28.bit b/libtoprammer/bit/atmega8dip28.bit new file mode 100644 index 0000000..8fb5846 Binary files /dev/null and b/libtoprammer/bit/atmega8dip28.bit differ diff --git a/libtoprammer/bit/build.sh b/libtoprammer/bit/build.sh new file mode 100755 index 0000000..b1dc553 --- /dev/null +++ b/libtoprammer/bit/build.sh @@ -0,0 +1,112 @@ +#!/bin/bash +# Rebuild FPGA bit files +# Copyright (c) 2010 Michael Buesch +# Licensed under the GNU/GPL v2+ + +basedir="$PWD/$(dirname $0)" +srcdir="$basedir/src" +bindir="$basedir" +bitparser="python $basedir/../bitfile.py" + +function terminate +{ + echo "Interrupted." + exit 1 +} + +trap terminate TERM INT + +function usage +{ + echo "Usage: build.sh [OPTIONS] [TARGETS]" + echo + echo "Options:" + echo " -h|--help Show this help text" + echo " -v|--verbose Verbose build" + echo + echo "Targets:" + echo "Specify the names of the targets to build, or leave blank to rebuild all." +} + +# Parse commandline +verbose=0 +nr_targets=0 +while [ $# -gt 0 ]; do + if [ "$1" = "-h" -o "$1" = "--help" ]; then + usage + exit 0 + fi + if [ "$1" = "-v" -o "$1" = "--verbose" ]; then + verbose=1 + shift + continue + fi + targets[nr_targets]="$1" + let nr_targets=nr_targets+1 + shift +done + +function should_build # $1=target +{ + target="$1" + [ "$target" = "template" ] && return 1 + [ $nr_targets -eq 0 ] && return 0 + let end=nr_targets-1 + for i in $(seq 0 $end); do + [ ${targets[i]} = "$target" ] && return 0 + done + return 1 +} + +# Check if the payload of two bitfiles matches +function bitfile_is_equal # $1=file1, $2=file2 +{ + [ -r $1 -a -r $2 ] || return 1 + sum1="$($bitparser $1 GETPAYLOAD | sha1sum - | cut -d' ' -f1)" + sum2="$($bitparser $2 GETPAYLOAD | sha1sum - | cut -d' ' -f1)" + [ "$sum1" = "$sum2" ] +} + +for src in $srcdir/*; do + [ -d "$src" ] || continue + + srcname="$(basename $src)" + logfile="$bindir/$srcname.build.log" + + should_build $srcname || continue + + echo "Building $srcname..." + make -C $src/ clean >/dev/null + if [ $? -ne 0 ]; then + echo "FAILED to clean $srcname." + exit 1 + fi + if [ $verbose -eq 0 ]; then + make -C $src/ all >$logfile + if [ $? -ne 0 ]; then + cat $logfile + echo "FAILED to build $srcname." + exit 1 + fi + cat $logfile | grep WARNING + else + make -C $src/ all + fi + + new="$src/$srcname.bit" + old="$bindir/$srcname.bit" + if bitfile_is_equal "$old" "$new"; then + echo "Bitfile for target $srcname did not change" + else + cp -f "$new" "$old" + fi + make -C $src/ clean >/dev/null + if [ $? -ne 0 ]; then + echo "FAILED to clean $srcname." + exit 1 + fi + rm -f $logfile +done +echo "Successfully built all images." + +exit 0 diff --git a/libtoprammer/bit/m2764a.bit b/libtoprammer/bit/m2764a.bit new file mode 100644 index 0000000..3f1fc18 Binary files /dev/null and b/libtoprammer/bit/m2764a.bit differ diff --git a/libtoprammer/bit/m8c-issp.bit b/libtoprammer/bit/m8c-issp.bit new file mode 100644 index 0000000..fc1f354 Binary files /dev/null and b/libtoprammer/bit/m8c-issp.bit differ diff --git a/libtoprammer/bit/src/.gitignore b/libtoprammer/bit/src/.gitignore new file mode 100644 index 0000000..e5aa91f --- /dev/null +++ b/libtoprammer/bit/src/.gitignore @@ -0,0 +1,26 @@ +__xst/ +__ngo/ + +*.bgn +*.bit +*.bld +*.drc +*_map.map +*_map.mrp +*_map.ncd +*_map.ngm +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*_pad.csv +*_pad.txt +*.par +*.pcf +*.srp +*.unroutes +*_usage.xml +*_summary.xml +*.xpi +*.twr diff --git a/libtoprammer/bit/src/atmega32dip40/Makefile b/libtoprammer/bit/src/atmega32dip40/Makefile new file mode 100644 index 0000000..62d5914 --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = atmega32dip40 +SRCS = $(NAME).v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj new file mode 100644 index 0000000..7f9b373 --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.prj @@ -0,0 +1 @@ +verilog work "atmega32dip40.v" diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v new file mode 100644 index 0000000..f547d71 --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.v @@ -0,0 +1,202 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Mega32 DIP40 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module atmega32dip40(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + // Read output-enable + wire read_oe; + // Signals to/from the DUT + reg dut_oe, dut_wr, dut_xtal, dut_pagel; + reg dut_bs1, dut_bs2; + reg dut_xa0, dut_xa1; + reg [7:0] dut_data; + // Cached address value + reg [7:0] address; + // Cached read data + reg [7:0] read_data; + // Constant lo/hi + wire low, high; + + assign low = 0; + assign high = 1; + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin + /* Nothing */ + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4: begin + dut_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6: begin + dut_xa1 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + 9: begin + dut_pagel <= data[7]; + end + 10: begin + dut_bs2 <= data[7]; + end + endcase + end + 8'h1B: begin + /* Nothing */ + end + 8'h1D: begin + /* Nothing */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data <= zif[32:25]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[39]; /* RDY */ + read_data[7:1] <= 0; + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], dut_pagel, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); + bufif0(zif[21], low, low); + bufif0(zif[22], low, low); + bufif0(zif[23], low, low); + bufif0(zif[24], dut_bs2, low); + bufif0(zif[25], dut_data[0], !dut_oe); + bufif0(zif[26], dut_data[1], !dut_oe); + bufif0(zif[27], dut_data[2], !dut_oe); + bufif0(zif[28], dut_data[3], !dut_oe); + bufif0(zif[29], dut_data[4], !dut_oe); + bufif0(zif[30], dut_data[5], !dut_oe); + bufif0(zif[31], dut_data[6], !dut_oe); + bufif0(zif[32], dut_data[7], !dut_oe); + bufif0(zif[33], low, high); + bufif0(zif[34], low, high); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], dut_xtal, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, high); + bufif0(zif[40], dut_oe, low); + bufif0(zif[41], dut_wr, low); + bufif0(zif[42], dut_bs1, low); + bufif0(zif[43], dut_xa0, low); + bufif0(zif[44], dut_xa1, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst new file mode 100644 index 0000000..fe2a54d --- /dev/null +++ b/libtoprammer/bit/src/atmega32dip40/atmega32dip40.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn atmega32dip40.prj +-ifmt mixed +-ofn atmega32dip40 +-ofmt NGC +-p xc2s15-5-vq100 +-top atmega32dip40 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso atmega32dip40.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/atmega88dip28/Makefile b/libtoprammer/bit/src/atmega88dip28/Makefile new file mode 100644 index 0000000..ae94a7f --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = atmega88dip28 +SRCS = $(NAME).v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.lso b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.prj b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.prj new file mode 100644 index 0000000..295880e --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.prj @@ -0,0 +1 @@ +verilog work "atmega88dip28.v" diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ucf b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ut b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.v b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.v new file mode 100644 index 0000000..2898dbb --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.v @@ -0,0 +1,203 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Mega88 DIP28 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module atmega88dip28(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + // Read output-enable + wire read_oe; + // Signals to/from the DUT + reg dut_oe, dut_wr, dut_xtal, dut_pagel; + reg dut_bs1, dut_bs2; + reg dut_xa0, dut_xa1; + reg [7:0] dut_data; + // Cached address value + reg [7:0] address; + // Cached read data + reg [7:0] read_data; + // Constant lo/hi + wire low, high; + + assign low = 0; + assign high = 1; + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin + /* Nothing */ + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4: begin + dut_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6: begin + dut_xa1 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + 9: begin + dut_pagel <= data[7]; + end + 10: begin + dut_bs2 <= data[7]; + end + endcase + end + 8'h1B: begin + /* Nothing */ + end + 8'h1D: begin + /* Nothing */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[5:0] <= zif[29:24]; + read_data[7:6] <= zif[34:33]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[13]; /* RDY */ + read_data[7:1] <= 0; + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, high); + bufif0(zif[14], dut_oe, low); + bufif0(zif[15], dut_wr, low); + bufif0(zif[16], dut_bs1, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], dut_xtal, low); + bufif0(zif[20], low, low); + bufif0(zif[21], dut_xa0, low); + bufif0(zif[22], dut_xa1, low); + bufif0(zif[23], dut_pagel, low); + bufif0(zif[24], dut_data[0], !dut_oe); + bufif0(zif[25], dut_data[1], !dut_oe); + bufif0(zif[26], dut_data[2], !dut_oe); + bufif0(zif[27], dut_data[3], !dut_oe); + bufif0(zif[28], dut_data[4], !dut_oe); + bufif0(zif[29], dut_data[5], !dut_oe); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], dut_data[6], !dut_oe); + bufif0(zif[34], dut_data[7], !dut_oe); + bufif0(zif[35], dut_bs2, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/atmega88dip28/atmega88dip28.xst b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.xst new file mode 100644 index 0000000..e602aa8 --- /dev/null +++ b/libtoprammer/bit/src/atmega88dip28/atmega88dip28.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn atmega88dip28.prj +-ifmt mixed +-ofn atmega88dip28 +-ofmt NGC +-p xc2s15-5-vq100 +-top atmega88dip28 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso atmega88dip28.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/atmega8dip28/Makefile b/libtoprammer/bit/src/atmega8dip28/Makefile new file mode 100644 index 0000000..0a8ce4b --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = atmega8dip28 +SRCS = atmega8dip28.v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj new file mode 100644 index 0000000..25c6746 --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.prj @@ -0,0 +1 @@ +verilog work "atmega8dip28.v" diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf new file mode 100644 index 0000000..7089175 --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +#NET "osc" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; \ No newline at end of file diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v new file mode 100644 index 0000000..77b4d7f --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.v @@ -0,0 +1,202 @@ +/* + * TOP2049 Open Source programming suite + * + * Atmel Mega8 DIP28 + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +module atmega8dip28(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + // Read output-enable + wire read_oe; + // Signals to/from the DUT + reg dut_oe, dut_wr, dut_xtal, dut_pagel; + reg dut_bs1, dut_bs2; + reg dut_xa0, dut_xa1; + reg [7:0] dut_data; + // Cached address value + reg [7:0] address; + // Cached read data + reg [7:0] read_data; + // Constant lo/hi + wire low, high; + + assign low = 0; + assign high = 1; + + always @(negedge ale) begin + address <= data; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h11: begin + /* Nothing */ + end + 8'h12: begin + /* Control pin access */ + case (data[6:0]) + 1: begin + /* Unused */ + end + 2: begin + dut_oe <= data[7]; + end + 3: begin + dut_wr <= data[7]; + end + 4: begin + dut_bs1 <= data[7]; + end + 5: begin + dut_xa0 <= data[7]; + end + 6: begin + dut_xa1 <= data[7]; + end + 7: begin + dut_xtal <= data[7]; + end + 8: begin + /* Unused */ + end + 9: begin + dut_pagel <= data[7]; + end + 10: begin + dut_bs2 <= data[7]; + end + endcase + end + 8'h1B: begin + /* Nothing */ + end + 8'h1D: begin + /* Nothing */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[5:0] <= zif[29:24]; + read_data[7:6] <= zif[34:33]; + end + 8'h12: begin + /* Status read */ + read_data[0] <= zif[13]; /* RDY */ + read_data[7:1] <= 0; + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, high); + bufif0(zif[12], low, low); + bufif0(zif[13], low, high); + bufif0(zif[14], dut_oe, low); + bufif0(zif[15], dut_wr, low); + bufif0(zif[16], dut_bs1, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], dut_xtal, low); + bufif0(zif[20], low, low); + bufif0(zif[21], dut_xa0, low); + bufif0(zif[22], dut_xa1, low); + bufif0(zif[23], dut_pagel, low); + bufif0(zif[24], dut_data[0], !dut_oe); + bufif0(zif[25], dut_data[1], !dut_oe); + bufif0(zif[26], dut_data[2], !dut_oe); + bufif0(zif[27], dut_data[3], !dut_oe); + bufif0(zif[28], dut_data[4], !dut_oe); + bufif0(zif[29], dut_data[5], !dut_oe); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], dut_data[6], !dut_oe); + bufif0(zif[34], dut_data[7], !dut_oe); + bufif0(zif[35], dut_bs2, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst new file mode 100644 index 0000000..dd040ec --- /dev/null +++ b/libtoprammer/bit/src/atmega8dip28/atmega8dip28.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn atmega8dip28.prj +-ifmt mixed +-ofn atmega8dip28 +-ofmt NGC +-p xc2s15-5-vq100 +-top atmega8dip28 +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso atmega8dip28.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/create.sh b/libtoprammer/bit/src/create.sh new file mode 100755 index 0000000..cce46db --- /dev/null +++ b/libtoprammer/bit/src/create.sh @@ -0,0 +1,29 @@ +#!/bin/bash + +basedir="$PWD/$(dirname $0)" +template="$basedir/template" + +set -e + +function usage +{ + echo "Usage: create.sh TARGET_NAME" +} + +if [ $# -ne 1 ]; then + usage + exit 1 +fi +name="$1" + +target="$basedir/$name" + +mkdir -p "$target" +for file in $(ls $template); do + suffix="$(echo $file | cut -d. -f2)" + targetfile="$name.$suffix" + [ $file != Makefile ] || targetfile=$file + cat $template/$file | sed -e 's/template/'$name'/' >$target/$targetfile +done + +exit 0 diff --git a/libtoprammer/bit/src/m2764a/Makefile b/libtoprammer/bit/src/m2764a/Makefile new file mode 100644 index 0000000..11e150d --- /dev/null +++ b/libtoprammer/bit/src/m2764a/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = m2764a +SRCS = $(NAME).v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/m2764a/m2764a.lso b/libtoprammer/bit/src/m2764a/m2764a.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/m2764a/m2764a.prj b/libtoprammer/bit/src/m2764a/m2764a.prj new file mode 100644 index 0000000..25e4d2c --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.prj @@ -0,0 +1 @@ +verilog work "m2764a.v" diff --git a/libtoprammer/bit/src/m2764a/m2764a.ucf b/libtoprammer/bit/src/m2764a/m2764a.ucf new file mode 100644 index 0000000..17f86dc --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/m2764a/m2764a.ut b/libtoprammer/bit/src/m2764a/m2764a.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/m2764a/m2764a.v b/libtoprammer/bit/src/m2764a/m2764a.v new file mode 100644 index 0000000..0082961 --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.v @@ -0,0 +1,246 @@ +/* + * TOP2049 Open Source programming suite + * + * M2764A EPROM + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module m2764a(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 12MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + /* Programmer context */ + reg [1:0] prog_busy; + reg [3:0] prog_command; + reg [3:0] prog_state; + reg [7:0] prog_pulselen; + reg [7:0] prog_count; + `define PROG_PPULSE 1 + + /* DUT signals */ + reg [12:0] dut_addr; + reg [7:0] dut_data; + reg dut_E; + reg dut_P; + reg dut_G; + + assign low = 0; + assign high = 1; + + initial begin + prog_busy <= 0; + prog_command <= 0; + prog_state <= 0; + prog_pulselen <= 0; + prog_count <= 0; + dut_addr <= 0; + dut_data <= 0; + dut_E <= 1; + dut_P <= 1; + dut_G <= 1; + end + + /* The delay counter. Based on the 12MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + always @(posedge osc) begin + if (delay_count == 0) begin + if (prog_busy[0] != prog_busy[1]) begin + /* busy0 != busy1 indicates that a command is running. + * Continue executing it... */ + + case (prog_command) + `PROG_PPULSE: begin + case (prog_state) + 0: begin /* Init */ + dut_P <= 0; + prog_count <= prog_pulselen - 1; + prog_state <= 1; + delay_count <= 24000 - 2; + end + 1: begin /* Delay loop */ + if (prog_count == 0) begin + /* Done */ + dut_P <= 1; + prog_state <= 0; + prog_busy[1] <= prog_busy[0]; + end else begin + prog_state <= 2; + delay_count <= 24000 - 2; + end + end + 2: begin + prog_count <= prog_count - 1; + prog_state <= 1; + end + endcase + end + endcase + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + dut_data <= data; + end + 8'h12: begin + /* Run a command. */ + prog_command <= data; + prog_busy[0] <= ~prog_busy[1]; + end + 8'h13: begin + /* Set addr low */ + dut_addr[7:0] <= data; + end + 8'h14: begin + /* Set addr high */ + dut_addr[12:8] <= data[4:0]; + end + 8'h15: begin + /* Set P pulse len */ + prog_pulselen <= data; + end + 8'h16: begin + /* Set E/G */ + dut_E <= data[0]; + dut_G <= data[1]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + read_data[2:0] <= zif[23:21]; + read_data[7:3] <= zif[29:25]; + end + 8'h12: begin + /* Read status */ + read_data[0] <= (prog_busy[0] != prog_busy[1]); + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, high); /* VPP */ + bufif0(zif[12], dut_addr[12], low); /* A12 */ + bufif0(zif[13], dut_addr[7], low); /* A7 */ + bufif0(zif[14], dut_addr[6], low); /* A6 */ + bufif0(zif[15], dut_addr[5], low); /* A5 */ + bufif0(zif[16], dut_addr[4], low); /* A4 */ + bufif0(zif[17], dut_addr[3], low); /* A3 */ + bufif0(zif[18], dut_addr[2], low); /* A2 */ + bufif0(zif[19], dut_addr[1], low); /* A1 */ + bufif0(zif[20], dut_addr[0], low); /* A0 */ + bufif0(zif[21], dut_data[0], !dut_G); /* Q0 */ + bufif0(zif[22], dut_data[1], !dut_G); /* Q1 */ + bufif0(zif[23], dut_data[2], !dut_G); /* Q2 */ + bufif0(zif[24], low, low); /* Vss */ + bufif0(zif[25], dut_data[3], !dut_G); /* Q3 */ + bufif0(zif[26], dut_data[4], !dut_G); /* Q4 */ + bufif0(zif[27], dut_data[5], !dut_G); /* Q5 */ + bufif0(zif[28], dut_data[6], !dut_G); /* Q6 */ + bufif0(zif[29], dut_data[7], !dut_G); /* Q7 */ + bufif0(zif[30], dut_E, low); /* E */ + bufif0(zif[31], dut_addr[10], low); /* A10 */ + bufif0(zif[32], dut_G, low); /* G */ + bufif0(zif[33], dut_addr[11], low); /* A11 */ + bufif0(zif[34], dut_addr[9], low); /* A9 */ + bufif0(zif[35], dut_addr[8], low); /* A8 */ + bufif0(zif[36], low, low); /* NC */ + bufif0(zif[37], dut_P, low); /* P */ + bufif0(zif[38], high, low); /* Vcc */ + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/m2764a/m2764a.xst b/libtoprammer/bit/src/m2764a/m2764a.xst new file mode 100644 index 0000000..bf215df --- /dev/null +++ b/libtoprammer/bit/src/m2764a/m2764a.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn m2764a.prj +-ifmt mixed +-ofn m2764a +-ofmt NGC +-p xc2s15-5-vq100 +-top m2764a +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso m2764a.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/m8c-issp/Makefile b/libtoprammer/bit/src/m8c-issp/Makefile new file mode 100644 index 0000000..96da03b --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = m8c-issp +SRCS = m8c-issp.v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.lso b/libtoprammer/bit/src/m8c-issp/m8c-issp.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.prj b/libtoprammer/bit/src/m8c-issp/m8c-issp.prj new file mode 100644 index 0000000..9394251 --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.prj @@ -0,0 +1 @@ +verilog work "m8c-issp.v" diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf b/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf new file mode 100644 index 0000000..17f86dc --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.ut b/libtoprammer/bit/src/m8c-issp/m8c-issp.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.v b/libtoprammer/bit/src/m8c-issp/m8c-issp.v new file mode 100644 index 0000000..7ed28fa --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.v @@ -0,0 +1,417 @@ +/* + * TOP2049 Open Source programming suite + * + * Cypress M8C In System Serial Programmer + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module m8c_issp(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 12MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + /* The M8C programmer context */ + `define ISSP_VEC_SIZE 22 /* bits */ + reg [1:0] issp_busy; /* Busy state. We're busy, if bits are unequal */ + reg [7:0] issp_command; /* Currently loaded command */ + reg [`ISSP_VEC_SIZE-1:0] issp_vector; /* Currently loaded output vector */ + reg [`ISSP_VEC_SIZE-1:0] issp_input_mask; /* Vector input bits mask */ + reg [`ISSP_VEC_SIZE-1:0] issp_input_vector; /* Read data */ + reg [5:0] issp_vecbit; /* Currently TXed/RXed bit */ + reg [7:0] issp_count; /* General purpose counter */ + reg [3:0] issp_state; /* Statemachine */ + + /* The M8C programmer commands */ + `define ISSPCMD_NONE 0 /* No command loaded */ + `define ISSPCMD_POR 1 /* Perform a power-on-reset */ + `define ISSPCMD_PWROFF 2 /* Turn power off */ + `define ISSPCMD_SENDVEC 3 /* Send the vector */ + `define ISSPCMD_EXEC 4 /* Do an "execute" transfer */ + + /* The M8C device signals */ + reg dut_sdata; + reg dut_sdata_input; + reg dut_sclk; + reg dut_sclk_z; + reg dut_vdd; + `define VDD_ON 0 + `define VDD_OFF 1 + `define ZIF_SDATA 22 /* SDATA ZIF pin */ + + assign low = 0; + assign high = 1; + + initial begin + issp_busy <= 0; + issp_command <= 0; + issp_vector <= 0; + issp_vecbit <= `ISSP_VEC_SIZE; + issp_state <= 0; + dut_sdata <= 0; + dut_sdata_input <= 1; + dut_sclk <= 0; + dut_sclk_z <= 1; + dut_vdd <= `VDD_OFF; + read_data <= 0; + end + + /* The delay counter. Based on the 12MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + always @(posedge osc) begin + if (delay_count == 0) begin + if (issp_busy[0] != issp_busy[1]) begin + /* busy0 != busy1 indicates that a command is running. + * Continue executing it... */ + + if (issp_command == `ISSPCMD_POR) begin + case (issp_state) + 0: begin + /* Turn on power and wait vDDwait time */ + dut_vdd <= `VDD_ON; + dut_sclk_z <= 1; + dut_sclk <= 0; + dut_sdata_input <= 1; +// delay_count <= 24000 - 1; /* Wait 1ms */ + delay_count <= 12000 - 1; +// delay_count <= 5000 - 1; + issp_state <= 1; + end + 1: begin + if (zif[`ZIF_SDATA] == 1) begin + issp_state <= 2; + delay_count <= 6 - 1; /* Wait 250ns */ + end + end + 2: begin + if (zif[`ZIF_SDATA] == 0) begin + issp_state <= 3; + dut_sclk_z <= 0; + dut_sclk <= 0; + delay_count <= 6 - 1; /* Wait 250ns */ + end + end + 3: begin + if (issp_vecbit == 0) begin + dut_sdata_input <= 1; + issp_state <= 5; + end else begin + /* Ok, ready to send the next bit */ + dut_sclk_z <= 0; + dut_sdata_input <= 0; + dut_sdata <= issp_vector[issp_vecbit - 1]; + dut_sclk <= 1; + issp_state <= 4; + delay_count <= 6 - 1; /* Wait 250ns */ + end + end + 4: begin + dut_sclk <= 0; + issp_state <= 3; + issp_vecbit <= issp_vecbit - 1; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 5: begin + /* We're done. */ + issp_busy[1] <= issp_busy[0]; + issp_vecbit <= `ISSP_VEC_SIZE; + issp_state <= 0; + end + endcase + end + if (issp_command == `ISSPCMD_PWROFF) begin + dut_vdd <= `VDD_OFF; + dut_sdata_input <= 1; + dut_sclk_z <= 1; + /* We're done. */ + issp_busy[1] <= issp_busy[0]; + end + if (issp_command == `ISSPCMD_SENDVEC) begin + case (issp_state) + 0: begin + dut_sclk_z <= 0; + if (issp_input_mask[issp_vecbit - 1] == 0) begin + /* Send bit */ + dut_sdata_input <= 0; + dut_sdata <= issp_vector[issp_vecbit - 1]; + end + dut_sclk <= 1; + issp_state <= 1; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 1: begin + if (issp_input_mask[issp_vecbit - 1] != 0) begin + /* Receive bit */ + //FIXME? + dut_sdata_input <= 1; + issp_input_vector[issp_vecbit - 1] = zif[`ZIF_SDATA]; + end + dut_sclk <= 0; + issp_state <= 2; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 2: begin//FIXME? + if (issp_vecbit == 0) begin + /* We're done. */ + dut_sdata_input <= 1; + issp_busy[1] <= issp_busy[0]; + issp_vecbit <= `ISSP_VEC_SIZE; + issp_state <= 0; + end else begin + /* The next bit */ + issp_vecbit <= issp_vecbit - 1; + issp_state <= 0; + end + end + endcase + end + if (issp_command == `ISSPCMD_EXEC) begin + case (issp_state) + 0: begin /* Init */ + dut_sdata_input <= 1; + dut_sdata <= 0; + dut_sclk_z <= 0; + issp_count <= 40; + issp_state <= 1; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 1: begin /* Wait 40 cycles, set clk=hi */ + dut_sclk <= 1; + issp_state <= 2; + issp_count <= issp_count - 1; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 2: begin /* Wait 40 cycles, set clk=lo */ + dut_sclk <= 0; + if (issp_count == 0) + issp_state <= 3; + else + issp_state <= 1; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 3: begin /* Wait for SDATA=0, set clk=hi */ + dut_sclk <= 1; + dut_sdata_input <= 1; + dut_sdata <= 0; + if (zif[`ZIF_SDATA] == 0) begin + /* Ok, got it. Now send 40 zeros. */ + issp_count <= 39; + issp_state <= 5; + end else begin + issp_state <= 4; + end + delay_count <= 6 - 1; /* Wait 250ns */ + end + 4: begin /* Wait for SDATA=0, set clk=lo */ + dut_sclk <= 0; + issp_state <= 3; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 5: begin /* Send 40 zeros. set clk=lo */ + dut_sdata_input <= 0; + dut_sclk <= 0; + if (issp_count == 0) + issp_state <= 7; + else + issp_state <= 6; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 6: begin /* Send 40 zeros. set clk=hi */ + dut_sclk <= 1; + issp_count <= issp_count - 1; + issp_state <= 5; + delay_count <= 6 - 1; /* Wait 250ns */ + end + 7: begin /* finish */ + /* We're done. */ + issp_busy[1] <= issp_busy[0]; + dut_sdata_input <= 1; + issp_state <= 0; + end + endcase + end + end + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + /* Unused */ + end + 8'h12: begin + /* Load and execute command */ + issp_command <= data; + issp_busy[0] <= ~issp_busy[1]; + end + 8'h13: begin + /* Load vector low */ + issp_vector[7:0] <= data; + end + 8'h14: begin + /* Load vector med */ + issp_vector[15:8] <= data; + end + 8'h15: begin + /* Load vector high */ + issp_vector[21:16] <= data[5:0]; + end + 8'h16: begin + /* Load input mask low */ + issp_input_mask[7:0] <= data; + end + 8'h17: begin + /* Load input mask med */ + issp_input_mask[15:8] <= data; + end + 8'h18: begin + /* Load input mask high */ + issp_input_mask[21:16] <= data[5:0]; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + /* Unused */ + end + 8'h12: begin + /* Read status */ + read_data[0] <= (issp_busy[0] != issp_busy[1]); + end + 8'h13: begin + /* Read input vector low */ + read_data <= issp_input_vector[7:0]; + end + 8'h14: begin + /* Read input vector med */ + read_data <= issp_input_vector[15:8]; + end + 8'h15: begin + /* Read input vector high */ + read_data <= issp_input_vector[21:16]; + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + assign zif[20] = low; /* GND */ + assign zif[21] = high; /* VDD */ + bufif0(zif[`ZIF_SDATA], dut_sdata, dut_sdata_input); /* SDATA */ + bufif0(zif[23], dut_sclk, dut_sclk_z); /* SCLK */ + bufif0(zif[24], dut_vdd, low); /* VDDen */ + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], low, low); + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], low, low); + bufif0(zif[34], low, low); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/m8c-issp/m8c-issp.xst b/libtoprammer/bit/src/m8c-issp/m8c-issp.xst new file mode 100644 index 0000000..6261e47 --- /dev/null +++ b/libtoprammer/bit/src/m8c-issp/m8c-issp.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn m8c-issp.prj +-ifmt mixed +-ofn m8c-issp +-ofmt NGC +-p xc2s15-5-vq100 +-top m8c_issp +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso m8c-issp.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/template/Makefile b/libtoprammer/bit/src/template/Makefile new file mode 100644 index 0000000..3f6d22f --- /dev/null +++ b/libtoprammer/bit/src/template/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = template +SRCS = $(NAME).v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/template/template.lso b/libtoprammer/bit/src/template/template.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/template/template.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/template/template.prj b/libtoprammer/bit/src/template/template.prj new file mode 100644 index 0000000..32dbdd2 --- /dev/null +++ b/libtoprammer/bit/src/template/template.prj @@ -0,0 +1 @@ +verilog work "template.v" diff --git a/libtoprammer/bit/src/template/template.ucf b/libtoprammer/bit/src/template/template.ucf new file mode 100644 index 0000000..42bb7cc --- /dev/null +++ b/libtoprammer/bit/src/template/template.ucf @@ -0,0 +1,62 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/template/template.ut b/libtoprammer/bit/src/template/template.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/template/template.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/template/template.v b/libtoprammer/bit/src/template/template.v new file mode 100644 index 0000000..b25e086 --- /dev/null +++ b/libtoprammer/bit/src/template/template.v @@ -0,0 +1,158 @@ +/* + * TOP2049 Open Source programming suite + * + * XXXXXXXXXXXXXXXX + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module template(data, ale, write, read, osc_in, zif); + inout [7:0] data; + input ale; + input write; + input read; + input osc_in; /* 12MHz oscillator */ + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + wire low, high; /* Constant lo/hi */ + + assign low = 0; + assign high = 1; + + /* The delay counter. Based on the 12MHz input clock. */ + reg [15:0] delay_count; + wire osc; + IBUF osc_ibuf(.I(osc_in), .O(osc)); + + always @(posedge osc) begin + if (delay_count == 0) begin + + end else begin + delay_count <= delay_count - 1; + end + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + end + 8'h16: begin + /* Raw ZIF pin read access */ + read_data <= zif[8:1]; + end + 8'h17: begin + /* Raw ZIF pin read access */ + read_data <= zif[16:9]; + end + 8'h18: begin + /* Raw ZIF pin read access */ + read_data <= zif[24:17]; + end + 8'h19: begin + /* Raw ZIF pin read access */ + read_data <= zif[32:25]; + end + 8'h1A: begin + /* Raw ZIF pin read access */ + read_data <= zif[40:33]; + end + 8'h1B: begin + /* Raw ZIF pin read access */ + read_data <= zif[48:41]; + end + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif0(zif[1], low, low); + bufif0(zif[2], low, low); + bufif0(zif[3], low, low); + bufif0(zif[4], low, low); + bufif0(zif[5], low, low); + bufif0(zif[6], low, low); + bufif0(zif[7], low, low); + bufif0(zif[8], low, low); + bufif0(zif[9], low, low); + bufif0(zif[10], low, low); + bufif0(zif[11], low, low); + bufif0(zif[12], low, low); + bufif0(zif[13], low, low); + bufif0(zif[14], low, low); + bufif0(zif[15], low, low); + bufif0(zif[16], low, low); + bufif0(zif[17], low, low); + bufif0(zif[18], low, low); + bufif0(zif[19], low, low); + bufif0(zif[20], low, low); + bufif0(zif[21], low, low); + bufif0(zif[22], low, low); + bufif0(zif[23], low, low); + bufif0(zif[24], low, low); + bufif0(zif[25], low, low); + bufif0(zif[26], low, low); + bufif0(zif[27], low, low); + bufif0(zif[28], low, low); + bufif0(zif[29], low, low); + bufif0(zif[30], low, low); + bufif0(zif[31], low, low); + bufif0(zif[32], low, low); + bufif0(zif[33], low, low); + bufif0(zif[34], low, low); + bufif0(zif[35], low, low); + bufif0(zif[36], low, low); + bufif0(zif[37], low, low); + bufif0(zif[38], low, low); + bufif0(zif[39], low, low); + bufif0(zif[40], low, low); + bufif0(zif[41], low, low); + bufif0(zif[42], low, low); + bufif0(zif[43], low, low); + bufif0(zif[44], low, low); + bufif0(zif[45], low, low); + bufif0(zif[46], low, low); + bufif0(zif[47], low, low); + bufif0(zif[48], low, low); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/template/template.xst b/libtoprammer/bit/src/template/template.xst new file mode 100644 index 0000000..00b1958 --- /dev/null +++ b/libtoprammer/bit/src/template/template.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn template.prj +-ifmt mixed +-ofn template +-ofmt NGC +-p xc2s15-5-vq100 +-top template +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso template.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/src/unitest/Makefile b/libtoprammer/bit/src/unitest/Makefile new file mode 100644 index 0000000..695029c --- /dev/null +++ b/libtoprammer/bit/src/unitest/Makefile @@ -0,0 +1,37 @@ +BITGEN = bitgen +PAR = par +MAP = map +NGDBUILD = ngdbuild +XST = xst +MKDIR = mkdir + +PART = 2s15vq100-5 +NAME = unitest +SRCS = $(NAME).v + +%.bit: %.ncd + $(BITGEN) -f `basename $< .ncd`.ut $< + +%.ncd: %_map.ncd + $(PAR) -w -ol std -t 1 $< $@ `basename $< _map.ncd`.pcf + +%_map.ncd: %.ngd + $(MAP) -p $(PART) -cm area -pr b -k 4 -c 100 -o `basename $< .ngd`_map.ncd $< `basename $< .ngd`.pcf + +%.ngd: %.ngc + $(NGDBUILD) -aul -dd __ngo -uc `basename $< .ngc`.ucf -p $(PART) $< $@ + +%.ngc: %.xst $(SRCS) + $(MKDIR) -p __xst/tmp + $(XST) -ifn $< + +all: $(NAME).bit + +clean: + rm -Rf __ngo __xst *.bgn *.bit *.bld *.drc *_map.mrp \ + *_map.ncd *_map.ngm *.ncd *.ngc *.ngd *.ngr \ + *.pad *_pad.csv *_pad.txt *.par *.pcf *.srp \ + *.unroutes *_usage.xml *.xpi *_map.map *_summary.xml \ + *.twr *_details.xml + + diff --git a/libtoprammer/bit/src/unitest/unitest.lso b/libtoprammer/bit/src/unitest/unitest.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.lso @@ -0,0 +1 @@ +work diff --git a/libtoprammer/bit/src/unitest/unitest.prj b/libtoprammer/bit/src/unitest/unitest.prj new file mode 100644 index 0000000..6de4d45 --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.prj @@ -0,0 +1 @@ +verilog work "unitest.v" diff --git a/libtoprammer/bit/src/unitest/unitest.ucf b/libtoprammer/bit/src/unitest/unitest.ucf new file mode 100644 index 0000000..f60e77e --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.ucf @@ -0,0 +1,65 @@ +NET "data<0>" LOC = P30; +NET "data<1>" LOC = P31; +NET "data<2>" LOC = P32; +NET "data<3>" LOC = P34; +NET "data<4>" LOC = P40; +NET "data<5>" LOC = P41; +NET "data<6>" LOC = P43; +NET "data<7>" LOC = P44; + +NET "read" LOC = P45; +NET "write" LOC = P39; +#NET "osc_in" LOC = P46; +NET "ale" LOC = P36; + +#NET "txt" LOC = P52; #FIXME +#NET "rxt" LOC = P73; #FIXME + +NET "zif<1>" LOC = P21; +NET "zif<2>" LOC = P19; +NET "zif<3>" LOC = P17; +NET "zif<4>" LOC = P15; +NET "zif<5>" LOC = P10; +NET "zif<6>" LOC = P8; +NET "zif<7>" LOC = P6; +NET "zif<8>" LOC = P4; +NET "zif<9>" LOC = P98; +NET "zif<10>" LOC = P96; +NET "zif<11>" LOC = P93; +NET "zif<12>" LOC = P86; +NET "zif<13>" LOC = P83; +NET "zif<14>" LOC = P81; +NET "zif<15>" LOC = P74; +NET "zif<16>" LOC = P71; +NET "zif<17>" LOC = P69; +NET "zif<18>" LOC = P67; +NET "zif<19>" LOC = P65; +NET "zif<20>" LOC = P60; +NET "zif<21>" LOC = P58; +NET "zif<22>" LOC = P56; +NET "zif<23>" LOC = P54; +NET "zif<24>" LOC = P47; +NET "zif<25>" LOC = P53; +NET "zif<26>" LOC = P55; +NET "zif<27>" LOC = P57; +NET "zif<28>" LOC = P59; +NET "zif<29>" LOC = P62; +NET "zif<30>" LOC = P66; +NET "zif<31>" LOC = P68; +NET "zif<32>" LOC = P70; +NET "zif<33>" LOC = P72; +NET "zif<34>" LOC = P80; +NET "zif<35>" LOC = P82; +NET "zif<36>" LOC = P84; +NET "zif<37>" LOC = P87; +NET "zif<38>" LOC = P95; +NET "zif<39>" LOC = P97; +NET "zif<40>" LOC = P3; +NET "zif<41>" LOC = P5; +NET "zif<42>" LOC = P7; +NET "zif<43>" LOC = P9; +NET "zif<44>" LOC = P13; +NET "zif<45>" LOC = P16; +NET "zif<46>" LOC = P18; +NET "zif<47>" LOC = P20; +NET "zif<48>" LOC = P22; diff --git a/libtoprammer/bit/src/unitest/unitest.ut b/libtoprammer/bit/src/unitest/unitest.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/libtoprammer/bit/src/unitest/unitest.v b/libtoprammer/bit/src/unitest/unitest.v new file mode 100644 index 0000000..ee88bc8 --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.v @@ -0,0 +1,180 @@ +/* + * TOP2049 Open Source programming suite + * + * Universal device tester + * FPGA bottomhalf implementation + * + * Copyright (c) 2010 Michael Buesch + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +module unitest(data, ale, write, read, zif); + inout [7:0] data; + input ale; + input write; + input read; + inout [48:1] zif; + + /* Interface to the microcontroller */ + wire read_oe; /* Read output-enable */ + reg [7:0] address; /* Cached address value */ + reg [7:0] read_data; /* Cached read data */ + + /* ZIF pin controls */ + reg [47:0] zif_output_en; + reg [47:0] zif_output; + + initial begin + zif_output_en <= 0; + zif_output <= 0; + end + + always @(posedge write) begin + case (address) + 8'h10: begin + /* Data write */ + /* Unused */ + end + 8'h12: begin + zif_output_en[7:0] <= data; + end + 8'h13: begin + zif_output_en[15:8] <= data; + end + 8'h14: begin + zif_output_en[23:16] <= data; + end + 8'h15: begin + zif_output_en[31:24] <= data; + end + 8'h16: begin + zif_output_en[39:32] <= data; + end + 8'h17: begin + zif_output_en[47:40] <= data; + end + 8'h18: begin + zif_output[7:0] <= data; + end + 8'h19: begin + zif_output[15:8] <= data; + end + 8'h1A: begin + zif_output[23:16] <= data; + end + 8'h1B: begin + zif_output[31:24] <= data; + end + 8'h1C: begin + zif_output[39:32] <= data; + end + 8'h1D: begin + zif_output[47:40] <= data; + end + endcase + end + + always @(negedge read) begin + case (address) + 8'h10: begin + /* Data read */ + /* Unused */ + end + 8'h18: begin + read_data <= zif[8:1]; + end + 8'h19: begin + read_data <= zif[16:9]; + end + 8'h1A: begin + read_data <= zif[24:17]; + end + 8'h1B: begin + read_data <= zif[32:25]; + end + 8'h1C: begin + read_data <= zif[40:33]; + end + 8'h1D: begin + read_data <= zif[48:41]; + end + endcase + end + + always @(negedge ale) begin + address <= data; + end + + assign read_oe = !read && address[4]; + + bufif1(zif[1], zif_output[0], zif_output_en[0]); + bufif1(zif[2], zif_output[1], zif_output_en[1]); + bufif1(zif[3], zif_output[2], zif_output_en[2]); + bufif1(zif[4], zif_output[3], zif_output_en[3]); + bufif1(zif[5], zif_output[4], zif_output_en[4]); + bufif1(zif[6], zif_output[5], zif_output_en[5]); + bufif1(zif[7], zif_output[6], zif_output_en[6]); + bufif1(zif[8], zif_output[7], zif_output_en[7]); + bufif1(zif[9], zif_output[8], zif_output_en[8]); + bufif1(zif[10], zif_output[9], zif_output_en[9]); + bufif1(zif[11], zif_output[10], zif_output_en[10]); + bufif1(zif[12], zif_output[11], zif_output_en[11]); + bufif1(zif[13], zif_output[12], zif_output_en[12]); + bufif1(zif[14], zif_output[13], zif_output_en[13]); + bufif1(zif[15], zif_output[14], zif_output_en[14]); + bufif1(zif[16], zif_output[15], zif_output_en[15]); + bufif1(zif[17], zif_output[16], zif_output_en[16]); + bufif1(zif[18], zif_output[17], zif_output_en[17]); + bufif1(zif[19], zif_output[18], zif_output_en[18]); + bufif1(zif[20], zif_output[19], zif_output_en[19]); + bufif1(zif[21], zif_output[20], zif_output_en[20]); + bufif1(zif[22], zif_output[21], zif_output_en[21]); + bufif1(zif[23], zif_output[22], zif_output_en[22]); + bufif1(zif[24], zif_output[23], zif_output_en[23]); + bufif1(zif[25], zif_output[24], zif_output_en[24]); + bufif1(zif[26], zif_output[25], zif_output_en[25]); + bufif1(zif[27], zif_output[26], zif_output_en[26]); + bufif1(zif[28], zif_output[27], zif_output_en[27]); + bufif1(zif[29], zif_output[28], zif_output_en[28]); + bufif1(zif[30], zif_output[29], zif_output_en[29]); + bufif1(zif[31], zif_output[30], zif_output_en[30]); + bufif1(zif[32], zif_output[31], zif_output_en[31]); + bufif1(zif[33], zif_output[32], zif_output_en[32]); + bufif1(zif[34], zif_output[33], zif_output_en[33]); + bufif1(zif[35], zif_output[34], zif_output_en[34]); + bufif1(zif[36], zif_output[35], zif_output_en[35]); + bufif1(zif[37], zif_output[36], zif_output_en[36]); + bufif1(zif[38], zif_output[37], zif_output_en[37]); + bufif1(zif[39], zif_output[38], zif_output_en[38]); + bufif1(zif[40], zif_output[39], zif_output_en[39]); + bufif1(zif[41], zif_output[40], zif_output_en[40]); + bufif1(zif[42], zif_output[41], zif_output_en[41]); + bufif1(zif[43], zif_output[42], zif_output_en[42]); + bufif1(zif[44], zif_output[43], zif_output_en[43]); + bufif1(zif[45], zif_output[44], zif_output_en[44]); + bufif1(zif[46], zif_output[45], zif_output_en[45]); + bufif1(zif[47], zif_output[46], zif_output_en[46]); + bufif1(zif[48], zif_output[47], zif_output_en[47]); + + bufif1(data[0], read_data[0], read_oe); + bufif1(data[1], read_data[1], read_oe); + bufif1(data[2], read_data[2], read_oe); + bufif1(data[3], read_data[3], read_oe); + bufif1(data[4], read_data[4], read_oe); + bufif1(data[5], read_data[5], read_oe); + bufif1(data[6], read_data[6], read_oe); + bufif1(data[7], read_data[7], read_oe); +endmodule diff --git a/libtoprammer/bit/src/unitest/unitest.xst b/libtoprammer/bit/src/unitest/unitest.xst new file mode 100644 index 0000000..1fa414b --- /dev/null +++ b/libtoprammer/bit/src/unitest/unitest.xst @@ -0,0 +1,57 @@ +set -tmpdir __xst/tmp +set -xsthdpdir __xst +run +-ifn unitest.prj +-ifmt mixed +-ofn unitest +-ofmt NGC +-p xc2s15-5-vq100 +-top unitest +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso unitest.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract YES +-resource_sharing YES +-async_to_sync NO +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/libtoprammer/bit/unitest.bit b/libtoprammer/bit/unitest.bit new file mode 100644 index 0000000..376fc50 Binary files /dev/null and b/libtoprammer/bit/unitest.bit differ diff --git a/libtoprammer/bitfile.py b/libtoprammer/bitfile.py new file mode 100644 index 0000000..f728e56 --- /dev/null +++ b/libtoprammer/bitfile.py @@ -0,0 +1,165 @@ +""" +# *.BIT file parser +# +# Copyright (c) 2009 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +import sys +import pkg_resources + +class BitfileException(Exception): pass + +class Bitfile: + # Magic header + MAGIC = "\x00\x09\x0f\xf0\x0f\xf0\x0f\xf0\x0f\xf0\x00\x00\x01" + # Field IDs + FIELD_SRCFILE = 0x61 + FIELD_FPGA = 0x62 + FIELD_DATE = 0x63 + FIELD_TIME = 0x64 + FIELD_PAYLOAD = 0x65 + + def __init__(self): + self.filename = "" + self.srcfile = "" + self.fpga = "" + self.date = "" + self.time = "" + self.payload = "" + + def getFilename(self): + return self.filename + + def getSrcFile(self): + return self.srcfile + + def getFPGA(self): + return self.fpga + + def getDate(self): + return self.date + + def getTime(self): + return self.time + + def getPayload(self): + return self.payload + + def parseFile(self, filename): + try: + data = file(filename, "rb").read() + except (IOError), e: + raise BitfileException("Failed to read \"" + filename + "\": " + e.strerror) + self.filename = filename + self.__parse(data) + + def __parse(self, data): + try: + magic = data[0:len(self.MAGIC)] + if magic != self.MAGIC: + raise BitfileException("Invalid magic header") + i = len(self.MAGIC) + while i < len(data): + i += self.__parseNextField(data, i) + except (IndexError), e: + raise BitfileException("Failed to parse BIT file") + if not self.fpga: + raise BitfileException("No FPGA ID string found") + if not self.payload: + raise BitfileException("No payload found") + + def __parseNextField(self, data, i): + fieldId = ord(data[i + 0]) + if (fieldId == self.FIELD_SRCFILE): + data = self.__parse16bitField(data, i + 1) + self.srcfile = data.strip().strip("\x00") + return len(data) + 3 + if (fieldId == self.FIELD_FPGA): + data = self.__parse16bitField(data, i + 1) + self.fpga = data.strip().strip("\x00") + return len(data) + 3 + if (fieldId == self.FIELD_DATE): + data = self.__parse16bitField(data, i + 1) + self.date = data.strip().strip("\x00") + return len(data) + 3 + if (fieldId == self.FIELD_TIME): + data = self.__parse16bitField(data, i + 1) + self.time = data.strip().strip("\x00") + return len(data) + 3 + if (fieldId == self.FIELD_PAYLOAD): + self.payload = self.__parse32bitField(data, i + 1) + return len(self.payload) + 5 + raise BitfileException("Found unknown data field 0x%02X" % fieldId) + + def __parse16bitField(self, data, i): + fieldLen = (ord(data[i + 0]) << 8) | ord(data[i + 1]) + return data[i + 2 : i + 2 + fieldLen] + + def __parse32bitField(self, data, i): + fieldLen = (ord(data[i + 0]) << 24) | (ord(data[i + 1]) << 16) |\ + (ord(data[i + 2]) << 8) | ord(data[i + 3]) + return data[i + 4 : i + 4 + fieldLen] + +def __probeFile(fullpath): + try: + file(fullpath, "rb") + except (IOError), e: + return False + return True + +def bitfileFind(filename): + "Search some standard paths for a bitfile" + if not filename.endswith(".bit"): + filename += ".bit" + if __probeFile(filename): + return filename + paths = ( ".", "./libtoprammer/bit", ) + for path in paths: + fullpath = path + "/" + filename + if __probeFile(fullpath): + return fullpath + fullpath = pkg_resources.resource_filename("libtoprammer", "bit/" + filename) + if __probeFile(fullpath): + return fullpath + return None + +if __name__ == "__main__": + if len(sys.argv) != 3: + print "Usage: %s file.bit ACTION" + print "" + print "Actions:" + print " GETSRC - print the src-file field to stdout" + print " GETFPGA - print the fpga-type field to stdout" + print " GETDATE - print the date field to stdout" + print " GETTIME - print the time field to stdout" + print " GETPAYLOAD - print the payload field to stdout" + sys.exit(1) + filename = sys.argv[1] + action = sys.argv[2].upper() + + b = Bitfile() + b.parseFile(filename) + if action == "GETSRC": + sys.stdout.write(b.getSrcFile()) + if action == "GETFPGA": + sys.stdout.write(b.getFPGA()) + if action == "GETDATE": + sys.stdout.write(b.getDate()) + if action == "GETTIME": + sys.stdout.write(b.getTime()) + if action == "GETPAYLOAD": + sys.stdout.write(b.getPayload()) diff --git a/libtoprammer/chip.py b/libtoprammer/chip.py new file mode 100644 index 0000000..876c948 --- /dev/null +++ b/libtoprammer/chip.py @@ -0,0 +1,149 @@ +""" +# TOP2049 Open Source programming suite +# +# Chip support +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from util import * + + +supportedChips = [] + +class Chip: + def __init__(self, chipID, broken=False): + "The chipID is the ID string from the bitfile." + self.chipID = chipID + self.broken = broken + self.printPrefix = True + + def getID(self): + return self.chipID + + def isBroken(self): + return self.broken + + def setTOP(self, top): + self.top = top + + def printWarning(self, message, newline=True): + if self.printPrefix: + message = self.chipID + ": " + message + self.top.printWarning(message, newline) + self.printPrefix = newline + + def printInfo(self, message, newline=True): + if self.printPrefix: + message = self.chipID + ": " + message + self.top.printInfo(message, newline) + self.printPrefix = newline + + def printDebug(self, message, newline=True): + if self.printPrefix: + message = self.chipID + ": " + message + self.top.printDebug(message, newline) + self.printPrefix = newline + + def throwError(self, message): + raise TOPException(self.chipID + ": " + message) + + def progressMeterInit(self, message, nrSteps): + self.progressNrSteps = nrSteps + self.progressHave25 = False + self.progressHave50 = False + self.progressHave75 = False + self.printInfo(message + " [0%", newline=False) + + def progressMeterFinish(self): + if not self.progressNrSteps: + self.printInfo("...", newline=False) + self.printInfo("100%]") + + def progressMeter(self, step): + if step % (self.progressNrSteps // 32) == 0: + percent = (step * 100 // self.progressNrSteps) + if percent >= 25 and not self.progressHave25: + self.printInfo("25%", newline=False) + self.progressHave25 = True + elif percent >= 50 and not self.progressHave50: + self.printInfo("50%", newline=False) + self.progressHave50 = True + elif percent >= 75 and not self.progressHave75: + self.printInfo("75%", newline=False) + self.progressHave75 = True + else: + self.printInfo(".", newline=False) + + def initializeChip(self): + pass # Override me in the subclass, if required. + + def shutdownChip(self): + pass # Override me in the subclass, if required. + + def readSignature(self): + # Override me in the subclass, if required. + raise TOPException("Signature reading not supported on " + self.chipID) + + def erase(self): + # Override me in the subclass, if required. + raise TOPException("Chip erasing not supported on " + self.chipID) + + def readProgmem(self): + # Override me in the subclass, if required. + raise TOPException("Program memory reading not supported on " + self.chipID) + + def writeProgmem(self, image): + # Override me in the subclass, if required. + raise TOPException("Program memory writing not supported on " + self.chipID) + + def readEEPROM(self): + # Override me in the subclass, if required. + raise TOPException("EEPROM reading not supported on " + self.chipID) + + def writeEEPROM(self, image): + # Override me in the subclass, if required. + raise TOPException("EEPROM writing not supported on " + self.chipID) + + def readFuse(self): + # Override me in the subclass, if required. + raise TOPException("Fuse reading not supported on " + self.chipID) + + def writeFuse(self, image): + # Override me in the subclass, if required. + raise TOPException("Fuse writing not supported on " + self.chipID) + + def readLockbits(self): + # Override me in the subclass, if required. + raise TOPException("Lockbit reading not supported on " + self.chipID) + + def writeLockbits(self, image): + # Override me in the subclass, if required. + raise TOPException("Lockbit writing not supported on " + self.chipID) + +def chipFind(chipID): + for chip in supportedChips: + if chip.getID().lower() == chipID.lower(): + return chip + return None + +def dumpSupportedChips(fd): + for chip in supportedChips: + broken = "" + if chip.isBroken(): + broken = " (broken)" + fd.write("%20s%s\n" % (chip.getID(), broken)) diff --git a/libtoprammer/chip_atmega32dip40.py b/libtoprammer/chip_atmega32dip40.py new file mode 100644 index 0000000..d82591f --- /dev/null +++ b/libtoprammer/chip_atmega32dip40.py @@ -0,0 +1,41 @@ +""" +# TOP2049 Open Source programming suite +# +# Atmel Mega32 DIP40 support +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip_atmega_common import * + +# Note: Chip has to be inserted upside-down into the ZIF + +class Chip_ATMega32DIP40(Chip_ATMega_common): + def __init__(self): + Chip_ATMega_common.__init__(self, + chipID = "atmega32dip40", + signature = "\x1E\x95\x02", + presenceCheckLayout = 0x0043FF000000, + GNDLayout = (35,), + VCCXLayout = (34,), + VPPLayout = (5, 6, 7, 9, 11, 12, 13, 14, 15, 16, 18, 19, 24, 26, 30, 31, 32, 33), + flashPageSize = 64, + flashPages = 256, + eepromPageSize = 4, + eepromPages = 256) + +supportedChips.append(Chip_ATMega32DIP40()) diff --git a/libtoprammer/chip_atmega88dip28.py b/libtoprammer/chip_atmega88dip28.py new file mode 100644 index 0000000..baa498a --- /dev/null +++ b/libtoprammer/chip_atmega88dip28.py @@ -0,0 +1,40 @@ +""" +# TOP2049 Open Source programming suite +# +# Atmel Mega88 DIP28 support +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip_atmega_common import * + + +class Chip_ATMega88DIP28(Chip_ATMega_common): + def __init__(self): + Chip_ATMega_common.__init__(self, + chipID = "atmega88dip28", + signature = "\x1E\x93\x0A", + presenceCheckLayout = 0x00031F801000, + GNDLayout = (18,), + VCCXLayout = (17,), + VPPLayout = (5, 6, 7, 9, 11), + flashPageSize = 32, + flashPages = 128, + eepromPageSize = 4, + eepromPages = 128) + +supportedChips.append(Chip_ATMega88DIP28()) diff --git a/libtoprammer/chip_atmega8dip28.py b/libtoprammer/chip_atmega8dip28.py new file mode 100644 index 0000000..d0fc660 --- /dev/null +++ b/libtoprammer/chip_atmega8dip28.py @@ -0,0 +1,40 @@ +""" +# TOP2049 Open Source programming suite +# +# Atmel Mega8 DIP28 support +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip_atmega_common import * + + +class Chip_ATMega8DIP28(Chip_ATMega_common): + def __init__(self): + Chip_ATMega_common.__init__(self, + chipID = "atmega8dip28", + signature = "\x1E\x93\x07", + presenceCheckLayout = 0x00031F801000, + GNDLayout = (18,), + VCCXLayout = (17,), + VPPLayout = (5, 6, 7, 9, 11), + flashPageSize = 32, + flashPages = 128, + eepromPageSize = 4, + eepromPages = 128) + +supportedChips.append(Chip_ATMega8DIP28()) diff --git a/libtoprammer/chip_atmega_common.py b/libtoprammer/chip_atmega_common.py new file mode 100644 index 0000000..265cdaa --- /dev/null +++ b/libtoprammer/chip_atmega_common.py @@ -0,0 +1,511 @@ +""" +# TOP2049 Open Source programming suite +# +# Atmel Mega common support +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip import * + + +class Chip_ATMega_common(Chip): + # The Atmel Mega programming commands + CMD_CHIPERASE = 0x80 # Chip Erase + CMD_WRITEFUSE = 0x40 # Write Fuse Bits + CMD_WRITELOCK = 0x20 # Write Lock Bits + CMD_WRITEFLASH = 0x10 # Write Flash + CMD_WRITEEEPROM = 0x11 # Write EEPROM + CMD_READSIG = 0x08 # Read Signature bytes and Calibration byte + CMD_READFUSELOCK = 0x04 # Read Fuse and Lock bits + CMD_READFLASH = 0x02 # Read Flash + CMD_READEEPROM = 0x03 # Read EEPROM + + def __init__(self, chipID, signature, + presenceCheckLayout, + GNDLayout, VCCXLayout, VPPLayout, + flashPageSize, flashPages, + eepromPageSize, eepromPages, + ): + Chip.__init__(self, chipID) + self.signature = signature + self.presenceCheckLayout = presenceCheckLayout + self.GNDLayout = GNDLayout # List of GND ZIF pins + self.VCCXLayout = VCCXLayout # List of VCCX ZIF pins + self.VPPLayout = VPPLayout # List of VPP ZIF pins + self.flashPageSize = flashPageSize # Flash page size, in words + self.flashPages = flashPages # Nr of flash pages + self.eepromPageSize = eepromPageSize # EEPROM page size, in bytes + self.eepromPages = eepromPages # Nr of EEPROM pages + assert(eepromPageSize <= 64) + + def initializeChip(self): + self.printDebug("Initializing chip") + self.top.gnd.setLayoutPins(self.GNDLayout) + self.top.vccx.setLayoutPins( [] ) + self.top.vpp.setLayoutPins( [] ) + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(0) + self.top.cmdSetVPPVoltage(12) + + def shutdownChip(self): + self.printDebug("Shutdown chip") + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(5) + self.top.vccx.setLayoutPins( [] ) + self.top.vpp.setLayoutPins( [] ) + self.top.gnd.setLayoutPins( [] ) + + def readSignature(self): + self.__initPins() + + (signature, calibration) = self.__readSigAndCalib() + + return signature + + def erase(self): + self.__initPins() + + self.progressMeterInit("Erasing chip", 0) + self.__loadCommand(self.CMD_CHIPERASE) + self.__pulseWR() + self.__waitForRDY() + self.progressMeterFinish() + + def readProgmem(self): + self.__initPins() + + self.progressMeterInit("Reading Flash", self.flashPages) + image = "" + for page in range(0, self.flashPages): + self.progressMeter(page) + readWords = 0 + for word in range(0, self.flashPageSize): + self.__loadCommand(self.CMD_READFLASH) + self.__loadAddr((page * self.flashPageSize) + word) + self.__readWordToStatusReg() + readWords += 1 + if readWords >= 32: + image += self.top.cmdReadStatusReg() + readWords = 0 + if readWords: + data = self.top.cmdReadStatusReg() + image += data[0:readWords] + self.progressMeterFinish() + return image + + def writeProgmem(self, image): + flashBytes = self.flashPageSize * 2 * self.flashPages + if len(image) != flashBytes: + self.throwError("Invalid program memory image size %d (expected %d)" %\ + (len(image), flashBytes)) + self.__initPins() + + self.progressMeterInit("Writing Flash", self.flashPages) + for page in range(0, self.flashPages): + self.progressMeter(page) + for word in range(0, self.flashPageSize): + self.__loadCommand(self.CMD_WRITEFLASH) + addr = (page * self.flashPageSize) + word + self.__loadAddr(addr) + addr *= 2 + data = image[addr : addr + 2] + self.__loadData(ord(data[0]) | (ord(data[1]) << 8)) + self.__setBS1(1) + self.__pulsePAGEL() + self.__setBS1(0) + self.__pulseWR() + self.__waitForRDY() + self.progressMeterFinish() + + def readEEPROM(self): + self.__initPins() + + self.progressMeterInit("Reading EEPROM", self.eepromPages) + image = "" + for page in range(0, self.eepromPages): + self.progressMeter(page) + for byte in range(0, self.eepromPageSize): + self.__loadCommand(self.CMD_READEEPROM) + self.__loadAddr((page * self.eepromPageSize) + byte) + self.__readLowByteToStatusReg() + data = self.top.cmdReadStatusReg() + image += data[0:self.eepromPageSize] + self.progressMeterFinish() + return image + + def writeEEPROM(self, image): + eepromBytes = self.eepromPageSize * self.eepromPages + if len(image) != eepromBytes: + self.throwError("Invalid EEPROM image size %d (expected %d)" %\ + (len(image), eepromBytes)) + self.__initPins() + + self.progressMeterInit("Writing EEPROM", self.eepromPages) + for page in range(0, self.eepromPages): + self.progressMeter(page) + for byte in range(0, self.eepromPageSize): + self.__loadCommand(self.CMD_WRITEEEPROM) + addr = (page * self.eepromPageSize) + byte + self.__loadAddr(addr) + data = image[addr] + self.__loadDataLow(ord(data[0])) + self.__pulsePAGEL() + self.__setBS1(0) + self.__pulseWR() + self.__waitForRDY() + self.progressMeterFinish() + + def readFuse(self): + self.__initPins() + + self.progressMeterInit("Reading Fuse bits", 0) + (fuse, lock) = self.__readFuseAndLockBits() + self.progressMeterFinish() + return fuse + + def writeFuse(self, image): + if len(image) != 2: + self.throwError("Invalid Fuses image size %d (expected %d)" %\ + (len(image), 2)) + self.__initPins() + + self.progressMeterInit("Writing Fuse bits", 0) + self.__loadCommand(self.CMD_WRITEFUSE) + self.__setBS2(0) + self.__loadDataLow(ord(image[0])) + self.__pulseWR() + self.__waitForRDY() + self.__loadCommand(self.CMD_WRITEFUSE) + self.__loadDataLow(ord(image[1])) + self.__setBS1(1) + self.__pulseWR() + self.__waitForRDY() + self.progressMeterFinish() + + def readLockbits(self): + self.__initPins() + + self.progressMeterInit("Reading lock bits", 0) + (fuses, lockbits) = self.__readFuseAndLockBits() + self.progressMeterFinish() + + return lockbits + + def writeLockbits(self, image): + if len(image) != 1: + self.throwError("Invalid lock-bits image size %d (expected %d)" %\ + (len(image), 1)) + self.__initPins() + + self.progressMeterInit("Writing lock bits", 0) + self.__loadCommand(self.CMD_WRITELOCK) + self.__loadDataLow(ord(image[0])) + self.__pulseWR() + self.__waitForRDY() + self.progressMeterFinish() + + def __readSigAndCalib(self): + """Reads the signature and calibration bytes and returns them. + This function expects a DUT present and pins initialized.""" + signature = "" + calibration = "" + for addr in range(0, 4): + self.__loadCommand(self.CMD_READSIG) + self.__loadAddr(addr) + self.__readWordToStatusReg() + data = self.top.cmdReadStatusReg() + if addr <= 2: + signature += data[0] + calibration += data[1] + return (signature, calibration) + + def __readFuseAndLockBits(self): + """Reads the Fuse and Lock bits and returns them. + This function expects a DUT present and pins initialized.""" + self.__loadCommand(self.CMD_READFUSELOCK) + self.__setBS2(0) + self.__readWordToStatusReg() + self.__setBS2(1) + self.__readWordToStatusReg() + self.__setBS2(0) + data = self.top.cmdReadStatusReg() + fuses = data[0] + data[3] + lock = data[1] + return (fuses, lock) + + def __initPins(self): + """Initialize the pin voltages and logic.""" + self.top.vpp.setLayoutPins( [] ) + self.top.vccx.setLayoutPins( [] ) + self.top.queueCommand("\x0E\x28\x01\x00") + self.top.cmdFPGAWrite(0x1B, 0x00) + self.top.cmdSetVPPVoltage(0) + self.top.cmdSetVPPVoltage(12) + self.top.gnd.setLayoutPins(self.GNDLayout) + self.top.cmdSetVCCXVoltage(4.4) + + self.__setXA0(0) + self.__setXA1(0) + self.__setBS1(0) + self.__setWR(0) + self.top.flushCommands() + + self.top.gnd.setLayoutPins(self.GNDLayout) + self.top.vccx.setLayoutPins(self.VCCXLayout) + + self.top.cmdFPGAReadRaw(0x16) + self.top.cmdFPGAReadRaw(0x17) + self.top.cmdFPGAReadRaw(0x18) + self.top.cmdFPGAReadRaw(0x19) + self.top.cmdFPGAReadRaw(0x1A) + self.top.cmdFPGAReadRaw(0x1B) + stat = self.top.cmdReadStatusReg48() + if stat != self.presenceCheckLayout: + msg = "Did not detect chip. Please check connections. (0x%012X)" % stat + if self.top.getForceLevel() >= 2: + self.printWarning(msg) + else: + self.throwError(msg) + + self.top.queueCommand("\x19") + self.__setReadMode(0) + self.top.queueCommand("\x34") + self.__setReadMode(0) + self.__setOE(0) + self.__setWR(1) + self.__setXTAL1(0) + self.__setXA0(0) + self.__setXA1(0) + self.top.cmdFPGAWrite(0x12, 0x08) + self.__setBS1(0) + self.__setBS2(0) + self.__setPAGEL(0) + self.__pulseXTAL1(10) + self.top.queueCommand("\x19") + self.top.flushCommands() + + self.top.vpp.setLayoutPins(self.VPPLayout) + + self.top.queueCommand("\x34") + self.top.cmdFPGAWrite(0x12, 0x88) + self.__setOE(1) + self.top.cmdFlush() + + (signature, calibration) = self.__readSigAndCalib() + if signature != self.signature: + msg = "Unexpected device signature. " +\ + "Want %02X%02X%02X, but got %02X%02X%02X" % \ + (ord(self.signature[0]), ord(self.signature[1]), + ord(self.signature[2]), + ord(signature[0]), ord(signature[1]), + ord(signature[2])) + if self.top.getForceLevel() >= 1: + self.printWarning(msg) + else: + self.throwError(msg) + + self.top.cmdFlush(10) + self.top.queueCommand("\x0E\x1F\x00\x00") + self.top.delay(0.1) + stat = self.top.cmdReadStatusReg32() + if stat != 0xB9C80101: + self.throwError("read: Unexpected status value 0x%08X" % stat) + + def __readWordToStatusReg(self): + """Read a data word from the DUT into the status register.""" + self.__setReadMode(1) + self.__setBS1(0) + self.__setOE(0) + self.top.cmdFPGAReadByte() + self.__setBS1(1) + self.top.cmdFPGAReadByte() + self.__setOE(1) + self.__setReadMode(0) + + def __readLowByteToStatusReg(self): + """Read the low data byte from the DUT into the status register.""" + self.__setReadMode(1) + self.__setBS1(0) + self.__setOE(0) + self.top.cmdFPGAReadByte() + self.__setOE(1) + self.__setReadMode(0) + + def __readHighByteToStatusReg(self): + """Read the high data byte from the DUT into the status register.""" + self.__setReadMode(1) + self.__setBS1(1) + self.__setOE(0) + self.top.cmdFPGAReadByte() + self.__setOE(1) + self.__setReadMode(0) + + def __loadData(self, data): + """Load a data word.""" + self.__loadDataLow(data) + self.__loadDataHigh(data >> 8) + + def __loadDataLow(self, dataLow): + """Load the low data byte.""" + self.__setBS1(0) + self.__setXA0(1) + self.__setXA1(0) + self.top.cmdFPGAWrite(0x10, dataLow & 0xFF) + self.__pulseXTAL1() + + def __loadDataHigh(self, dataHigh): + """Load the high data byte.""" + self.__setBS1(1) + self.__setXA0(1) + self.__setXA1(0) + self.top.cmdFPGAWrite(0x10, dataHigh & 0xFF) + self.__pulseXTAL1() + + def __loadAddr(self, addr): + """Load an address word.""" + self.__loadAddrLow(addr) + self.__loadAddrHigh(addr >> 8) + + def __loadAddrLow(self, addrLow): + """Load the low address byte.""" + self.__setBS1(0) + self.__setXA0(0) + self.__setXA1(0) + self.top.cmdFPGAWrite(0x10, addrLow & 0xFF) + self.__pulseXTAL1() + + def __loadAddrHigh(self, addrHigh): + """Load the high address byte.""" + self.__setBS1(1) + self.__setXA0(0) + self.__setXA1(0) + self.top.cmdFPGAWrite(0x10, addrHigh & 0xFF) + self.__pulseXTAL1() + + def __loadCommand(self, command): + """Load a command into the device.""" + self.top.queueCommand("\x34") + self.__setBS1(0) + self.top.queueCommand("\x34") + self.__setXA0(0) + self.__setXA1(1) + self.top.cmdFPGAWrite(0x10, command) + self.__pulseXTAL1() + + def __setReadMode(self, high): + """Put the FPGA into read mode.""" + value = 0x01 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __waitForRDY(self): + """Wait for the RDY pin to go high.""" + self.top.delay(0.01) + for i in range(0, 50): + if self.__getRDY(): + return + self.top.delay(0.01) + self.throwError("Timeout waiting for READY signal from chip.") + + def __getRDY(self): + """Read the state of the RDY/BSY pin.""" + return bool(self.__getStatus() & 0x01) + + def __getStatus(self): + """Read the programmer status register""" + self.top.cmdFPGAReadRaw(0x12) + stat = self.top.cmdReadStatusReg() + return ord(stat[0]) + + def __setOE(self, high): + """Set the OE pin of the DUT""" + value = 0x02 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __setWR(self, high): + """Set the WR pin of the DUT""" + value = 0x03 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __pulseWR(self, count=1): + """Do a negative pulse on the WR pin of the DUT""" + while count > 0: + self.__setWR(0) + self.__setWR(1) + count -= 1 + + def __setBS1(self, high): + """Set the BS1 pin of the DUT""" + value = 0x04 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __setXA0(self, high): + """Set the XA0 pin of the DUT""" + value = 0x05 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __setXA1(self, high): + """Set the XA1 pin of the DUT""" + value = 0x06 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __setXTAL1(self, high): + """Set the XTAL1 pin of the DUT""" + value = 0x07 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __pulseXTAL1(self, count=1): + """Do a positive pulse on the XTAL1 pin of the DUT""" + while count > 0: + self.__setXTAL1(1) + self.__setXTAL1(0) + count -= 1 + + def __setPAGEL(self, high): + """Set the PAGEL pin of the DUT""" + value = 0x09 + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) + + def __pulsePAGEL(self, count=1): + """Do a positive pulse on the PAGEL pin of the DUT""" + while count > 0: + self.__setPAGEL(1) + self.__setPAGEL(0) + count -= 1 + + def __setBS2(self, high): + """Set the BS2 pin of the DUT""" + value = 0x0A + if high: + value |= 0x80 + self.top.cmdFPGAWrite(0x12, value) diff --git a/libtoprammer/chip_m2764a.py b/libtoprammer/chip_m2764a.py new file mode 100644 index 0000000..ca1aff9 --- /dev/null +++ b/libtoprammer/chip_m2764a.py @@ -0,0 +1,161 @@ +""" +# TOP2049 Open Source programming suite +# +# M2764A EPROM programmer +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip import * + + +class M2764A(Chip): + PROGCMD_PPULSE = 1 # Perform a P-pulse + + STAT_BUSY = 0x01 # Programmer is running a command + + def __init__(self): + Chip.__init__(self, "m2764a", broken=True) + + def initializeChip(self): + self.printDebug("Initializing chip") + self.top.vccx.setLayoutMask(0) + self.top.vpp.setLayoutMask(0) + self.top.gnd.setLayoutPins( [] ) + self.top.queueCommand("\x0E\x28\x01\x00") + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(0) + self.top.cmdSetVPPVoltage(5) + + def shutdownChip(self): + self.printDebug("Shutdown chip") + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(5) + self.top.vccx.setLayoutMask(0) + self.top.vpp.setLayoutMask(0) + self.top.gnd.setLayoutPins( [] ) + + def readEEPROM(self): + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(5) + self.top.vccx.setLayoutPins( (38,) ) + self.top.vpp.setLayoutPins( (5, 6, 7, 9, 11) ) + self.top.gnd.setLayoutPins( (24,) ) + + image = "" + self.progressMeterInit("Reading EPROM", 0x2000) + self.__setEG(E=1, G=1) + for addr in range(0, 0x2000): + self.progressMeter(addr) + image += self.__readData(addr) + self.__setEG(E=1, G=1) + self.progressMeterFinish() + + return image + + def writeEEPROM(self, image): + if len(image) != 0x2000: + self.throwError("Invalid EPROM image size %d (expected %d)" %\ + (len(image), 0x2000)) + + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(12) + self.top.vccx.setLayoutPins( (38,) ) + self.top.vpp.setLayoutPins( (5, 6, 7, 9, 11) ) + self.top.gnd.setLayoutPins( (24,) ) + + self.progressMeterInit("Writing EPROM", 0x2000) + self.__setEG(E=1, G=1) + for addr in range(0, 0x2000): + self.progressMeter(addr) + self.__writeData(addr, ord(image[addr])) + self.__setEG(E=1, G=1) + self.progressMeterFinish() + + def __readData(self, addr): + self.__loadAddr(addr) + self.__setEG(E=0, G=0) + self.top.cmdFPGAReadByte() + stat = self.top.cmdReadStatusReg() + return stat[0] + + def __writeData(self, addr, data): + self.__setEG(E=0, G=1) + self.__loadAddr(addr) + self.__loadData(data) + self.__loadPPulseLen(1) + self.__runCommandSync(self.PROGCMD_PPULSE) + for i in range(0, 25): + r = ord(self.__readData(addr)) + if r == data: + break + self.__setEG(E=0, G=1) + self.__runCommandSync(self.PROGCMD_PPULSE) + else: + self.throwError("Failed to program 0x%04X (got 0x%02X, expected 0x%02X)" %\ + (addr, r, data)) + self.__setEG(E=0, G=1) + self.__loadPPulseLen(3 * (i + 1)) + self.__runCommandSync(self.PROGCMD_PPULSE) + + def __loadData(self, data): + self.top.cmdFPGAWrite(0x10, data) + + def __loadCommand(self, command): + self.top.cmdFPGAWrite(0x12, command & 0xFF) + + def __runCommandSync(self, command): + self.__loadCommand(command) + self.__busyWait() + + def __loadAddrLow(self, addrLow): + self.top.cmdFPGAWrite(0x13, addrLow & 0xFF) + + def __loadAddrHigh(self, addrHigh): + self.top.cmdFPGAWrite(0x14, addrHigh & 0xFF) + + def __loadAddr(self, addr): + self.__loadAddrLow(addr) + self.__loadAddrHigh(addr >> 8) + + def __loadPPulseLen(self, msec): + self.top.cmdFPGAWrite(0x15, msec) + + def __setEG(self, E, G): + data = 0 + if E: + data |= 1 + if G: + data |= 2 + self.top.cmdFPGAWrite(0x16, data) + + def __getStatusFlags(self): + self.top.cmdFPGAReadRaw(0x12) + stat = self.top.cmdReadStatusReg() + return ord(stat[0]) + + def __busy(self): + return bool(self.__getStatusFlags() & self.STAT_BUSY) + + def __busyWait(self): + for i in range(0, 100): + if not self.__busy(): + return + self.top.delay(0.01) + self.throwError("Timeout in busywait.") + +supportedChips.append(M2764A()) diff --git a/libtoprammer/chip_m8cissp.py b/libtoprammer/chip_m8cissp.py new file mode 100644 index 0000000..3f23a54 --- /dev/null +++ b/libtoprammer/chip_m8cissp.py @@ -0,0 +1,347 @@ +""" +# TOP2049 Open Source programming suite +# +# Cypress M8C In System Serial Programmer +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip import * +import time + + +class M8C_ISSP(Chip): + ISSPCMD_POR = 1 # Perform a power-on-reset + ISSPCMD_PWROFF = 2 # Turn power off + ISSPCMD_SENDVEC = 3 # Send a vector + ISSPCMD_EXEC = 4 # Do an "execute" transfer + + STAT_BUSY = 0x01 # Programmer is running a command + + STRVEC_SETFREQ = { + 2 : "1001111110000000101000", + 3 : "1001111110000001001000", + 3.578 : "1001111110000001011000", + 4 : "1001111110000001101000", + 5 : "1001111110000010001000", + 6 : "1001111110000010101000", + 6.66666 : "1001111110000010111000", + 7 : "1001111110000011001000", + 8 : "1001111110000011100000", + 9 : "1001111110000100000000", + 10 : "1001111110000100100000", + 11 : "1001111110000101000000", + 12 : "1001111110000101100000", + } + STRVEC_INIT1 = ( + "1100101000000000000000", + "0000000000000000000000", + "0000000000000000000000", + "1000111101100100000000", + "1101111011100000000000", + "1101111011000001000000", + "1001111100000111010000", + "1001111100100001011000", + "1101111010100000000000", + "1101111010000000011000", + "1001111101100100000000", + "1101111100100110000000", + "1101111101001000000000", + "1101111000000001000000", + "1101111100000000000000", + "1101111111100010010000", + ) + STRVEC_INIT2 = ( + "1101111011100000000000", + "1101111011000001000000", + "1001111100000111010000", + "1001111100100001011000", + "1101111010100000000000", + "1101111010000000011000", + "1001111101100100000000", + "1101111100100110000000", + "1101111101001000000000", + "1001111101000000001000", + "1101111000000000110000", + "1101111100000000000000", + "1101111111100010010000", + ) + STRVEC_INIT3_HIVDD = ( + "1101111011100000000000", + "1101111010000000011000", + "1101111010100000000000", + "1101111011000001000000", + "1101111100001010001000", + "1101111100111111100000", + "1101111101000110000000", + "1101111111100010010000", + "0000000000000000000000", + "1101111011100000000000", + "1101111010000000011000", + "1101111010100000000000", + "1101111011000001000000", + "1101111100001100000000", + "1101111100111101010000", + "1101111101000110000000", + "1101111011100010000000", + "1101111111100010010000", + "0000000000000000000000", + ) + STRVEC_INIT3_LOVDD = ( + "1101111011100000000000", + "1101111010000000011000", + "1101111010100000000000", + "1101111011000001000000", + "1101111100001010001000", + "1101111100111111000000", + "1101111101000110000000", + "1101111111100010010000", + "0000000000000000000000", + "1101111011100000000000", + "1101111010000000011000", + "1101111010100000000000", + "1101111011000001000000", + "1101111100001100000000", + "1101111100111101010000", + "1101111101000110000000", + "1101111011100010000000", + "1101111111100010010000", + "0000000000000000000000", + ) + STRVEC_IDSETUP = ( + "1101111011100000000000", + "1101111011000001000000", + "1001111100000111010000", + "1001111100100001011000", + "1101111010100000000000", + "1101111010000000011000", + "1001111101100100000000", + "1101111100100110000000", + "1101111101001000000000", + "1001111101000000000000", + "1101111000000000110000", + "1101111100000000000000", + "1101111111100010010000", + ) + STRVEC_READBYTE = "101aaaaaaaaZDDDDDDDDZ0" + STRVEC_ERASEALL = ( + "1101111011100000000000", + "1101111011001000000000", + "1001111100000111010000", + "1001111100101000011000", + "1101111010100000000000", + "1101111010000000011000", + "1001111101110000000000", + "1101111100100110000000", + "1101111101001000000000", + "1101111000000000101000", + "1101111100000000000000", + "1101111111100010010000", + ) + STRVEC_SECURE = ( + "1101111011100000000000", + "1101111011001000000000", + "1001111100000111010000", + "1001111100101000011000", + "1101111010100000000000", + "1101111010000000011000", + "1001111101110000000000", + "1101111100100110000000", + "1101111101001000000000", + "1101111000000000100000", + "1101111100000000000000", + "1101111111100010010000", + ) + + def __init__(self): + Chip.__init__(self, "m8c-issp", broken=True) + + def initializeChip(self): + self.printDebug("Initializing chip") + self.top.vccx.setLayoutMask(0) + self.top.vpp.setLayoutMask(0) + self.top.gnd.setLayoutPins( [] ) + self.top.cmdSetVCCXVoltage(5) + self.top.cmdFlush() + self.top.cmdSetVPPVoltage(0) + self.top.cmdFlush() + self.top.cmdSetVPPVoltage(5) + + #XXX + self.__powerOnReset() + id = self.__readID() + print "ID=0x%04X" % id + + def shutdownChip(self): + self.printDebug("Shutdown chip") + self.top.cmdSetVCCXVoltage(5) + self.top.cmdFlush() + self.top.cmdSetVPPVoltage(5) + self.top.cmdFlush() + self.top.vccx.setLayoutMask(0) + self.top.vpp.setLayoutMask(0) + self.top.cmdFlush() + self.top.gnd.setLayoutPins( [] ) + + def __powerDown(self): + "Turn the power to the device off" + self.printDebug("Powering device down...") + self.__runCommandSync(self.ISSPCMD_PWROFF) + self.top.flushCommands() + time.sleep(3) + + def __powerOnReset(self): + "Perform a complete power-on-reset and initialization" + self.printDebug("Initializing supply power...") + self.top.gnd.setLayoutPins( (20,) ) + self.top.cmdFlush() + self.top.vccx.setLayoutPins( (21,) ) + self.top.cmdFlush() + self.top.cmdSetVCCXVoltage(5) + self.top.cmdFlush() + + self.__powerDown() + self.printDebug("Performing a power-on-reset...") + self.__loadStringVector(self.STRVEC_INIT1[0]) + self.__runCommandSync(self.ISSPCMD_POR) + self.printDebug("Sending vector 1...") + for vec in self.STRVEC_INIT1[1:]: + self.__loadStringVector(vec) + self.__runCommandSync(self.ISSPCMD_SENDVEC) + self.printDebug("Executing...") + self.__runCommandSync(self.ISSPCMD_EXEC) + self.printDebug("Sending vector 2...") + for vec in self.STRVEC_INIT2: + self.__loadStringVector(vec) + self.__runCommandSync(self.ISSPCMD_SENDVEC) + self.printDebug("Executing...") + self.__runCommandSync(self.ISSPCMD_EXEC) + self.printDebug("Sending vector 3...") + for vec in self.STRVEC_INIT3_HIVDD: + self.__loadStringVector(vec) + self.__runCommandSync(self.ISSPCMD_SENDVEC) + + def __readID(self): + "Read the silicon ID" + for vec in self.STRVEC_IDSETUP: + self.__loadStringVector(vec) + self.__runCommandSync(self.ISSPCMD_SENDVEC) + self.__runCommandSync(self.ISSPCMD_EXEC) + + low = self.__readByte(0xF8) + high = self.__readByte(0xF9) + + return low | (high << 8) + + def __readByte(self, address): + strVec = self.__stringVectorReplace(self.STRVEC_READBYTE, "a", address) + self.__loadStringVector(strVec) + self.__runCommandSync(self.ISSPCMD_SENDVEC) + input = self.__getInputVector() + return (input >> 2) & 0xFF + + def __loadCommand(self, command): + self.top.cmdFPGAWrite(0x12, command & 0xFF) + + def __runCommandSync(self, command): + self.__loadCommand(command) + self.__busyWait() + + def __loadVectorLow(self, vecLow): + self.top.cmdFPGAWrite(0x13, vecLow & 0xFF) + + def __loadVectorMed(self, vecMed): + self.top.cmdFPGAWrite(0x14, vecMed & 0xFF) + + def __loadVectorHigh(self, vecHigh): + self.top.cmdFPGAWrite(0x15, vecHigh & 0xFF) + + def __loadVector(self, vec): + self.__loadVectorLow(vec) + self.__loadVectorMed(vec >> 8) + self.__loadVectorHigh(vec >> 16) + + def __loadVectorInputMaskLow(self, maskLow): + self.top.cmdFPGAWrite(0x16, maskLow & 0xFF) + + def __loadVectorInputMaskMed(self, maskMed): + self.top.cmdFPGAWrite(0x17, maskMed & 0xFF) + + def __loadVectorInputMaskHigh(self, maskHigh): + self.top.cmdFPGAWrite(0x18, maskHigh & 0xFF) + + def __loadVectorInputMask(self, mask): + self.__loadVectorInputMaskLow(mask) + self.__loadVectorInputMaskMed(mask >> 8) + self.__loadVectorInputMaskHigh(mask >> 16) + + def __getStatusFlags(self): + self.top.cmdFPGAReadRaw(0x12) + stat = self.top.cmdReadStatusReg() + return ord(stat[0]) + + def __busy(self): + return bool(self.__getStatusFlags() & self.STAT_BUSY) + + def __busyWait(self): +#XXX for i in range(0, 50): + while 1: + if not self.__busy(): + return + time.sleep(0.01) + self.throwError("Timeout in busywait. Chip not responding?") + + def __getInputVector(self): + self.top.cmdFPGAReadRaw(0x13) + self.top.cmdFPGAReadRaw(0x14) + self.top.cmdFPGAReadRaw(0x15) + stat = self.top.cmdReadStatusReg() + return ord(stat[0]) | (ord(stat[1]) << 8) | (ord(stat[2]) << 16) + + def __stringVectorToBinary(self, vector): + binary = 0 + input = 0 + assert(len(vector) == 22) + bit = len(vector) - 1 + for b in vector: + if b == "1": + binary |= (1 << bit) + if b == "H" or b == "L" or b == "Z" or b == "D": + input |= (1 << bit) + bit -= 1 + return (binary, input) + + def __stringVectorReplace(self, strVec, replace, data): + ret = "" + for i in range(len(strVec) - 1, -1, -1): + b = strVec[i] + if b == replace: + if (data & 1): + ret = "1" + ret + else: + ret = "0" + ret + data >>= 1 + else: + ret = b + ret + return ret + + def __loadStringVector(self, strVec): + (vector, inputMask) = self.__stringVectorToBinary(strVec) + self.__loadVectorInputMask(inputMask) + self.__loadVector(vector) + +supportedChips.append(M8C_ISSP()) diff --git a/libtoprammer/chip_unitest.py b/libtoprammer/chip_unitest.py new file mode 100644 index 0000000..a5d65ae --- /dev/null +++ b/libtoprammer/chip_unitest.py @@ -0,0 +1,93 @@ +""" +# TOP2049 Open Source programming suite +# +# Universal device tester +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from chip import * + + +class Chip_Unitest(Chip): + def __init__(self): + Chip.__init__(self, "unitest") + + def initializeChip(self): + self.printDebug("Initializing chip") + self.__reset() + + def shutdownChip(self): + self.printDebug("Shutdown chip") + self.__reset() + + def __reset(self): + self.top.vccx.setLayoutPins( [] ) + self.top.vpp.setLayoutPins( [] ) + self.top.gnd.setLayoutPins( [] ) + self.top.cmdSetVCCXVoltage(5) + self.top.cmdSetVPPVoltage(0) + self.top.cmdSetVPPVoltage(5) + self.setOutputEnableMask(0) + self.setOutputs(0) + + def setVCCX(self, voltage, layout): + self.top.cmdSetVCCXVoltage(0) + self.top.cmdLoadVCCXLayout(layout) + self.top.cmdSetVCCXVoltage(voltage) + self.top.flushCommands() + + def setVPP(self, voltage, layout): + self.top.cmdSetVPPVoltage(0) + self.top.cmdLoadVPPLayout(layout) + self.top.cmdSetVPPVoltage(voltage) + self.top.flushCommands() + #TODO: Disable outen on these pins + + def setGND(self, pin): + self.top.cmdSetGNDPin(pin) + self.top.flushCommands() + + def setOutputEnableMask(self, mask): + self.top.cmdFPGAWrite(0x12, mask & 0xFF) + self.top.cmdFPGAWrite(0x13, (mask >> 8) & 0xFF) + self.top.cmdFPGAWrite(0x14, (mask >> 16) & 0xFF) + self.top.cmdFPGAWrite(0x15, (mask >> 24) & 0xFF) + self.top.cmdFPGAWrite(0x16, (mask >> 32) & 0xFF) + self.top.cmdFPGAWrite(0x17, (mask >> 40) & 0xFF) + self.top.flushCommands() + + def setOutputs(self, mask): + self.top.cmdFPGAWrite(0x18, mask & 0xFF) + self.top.cmdFPGAWrite(0x19, (mask >> 8) & 0xFF) + self.top.cmdFPGAWrite(0x1A, (mask >> 16) & 0xFF) + self.top.cmdFPGAWrite(0x1B, (mask >> 24) & 0xFF) + self.top.cmdFPGAWrite(0x1C, (mask >> 32) & 0xFF) + self.top.cmdFPGAWrite(0x1D, (mask >> 40) & 0xFF) + self.top.flushCommands() + + def getInputs(self): + self.top.cmdFPGAReadRaw(0x18) + self.top.cmdFPGAReadRaw(0x19) + self.top.cmdFPGAReadRaw(0x1A) + self.top.cmdFPGAReadRaw(0x1B) + self.top.cmdFPGAReadRaw(0x1C) + self.top.cmdFPGAReadRaw(0x1D) + inputs = self.top.cmdReadStatusReg48() + return inputs + +supportedChips.append(Chip_Unitest()) diff --git a/libtoprammer/top2049/__init__.py b/libtoprammer/top2049/__init__.py new file mode 100644 index 0000000..8d1c8b6 --- /dev/null +++ b/libtoprammer/top2049/__init__.py @@ -0,0 +1 @@ + diff --git a/libtoprammer/top2049/gnd_layouts.py b/libtoprammer/top2049/gnd_layouts.py new file mode 100644 index 0000000..4e48688 --- /dev/null +++ b/libtoprammer/top2049/gnd_layouts.py @@ -0,0 +1,66 @@ +""" +# TOP2049 Open Source programming suite +# +# TOP2049 GND layout definitions +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +class GNDLayout: + # A list of valid ZIF GND pins (0=none) + validPins = (0, 5, 14, 15, 16, 17, 18, 19, 20, 24, 26, 27, + 28, 29, 33, 34, 35) + + def __init__(self, top): + self.top = top + self.layouts = [] + for pin in self.validPins: + id = pin + if id != 0: + id -= 4 + mask = 0 + if pin != 0: + mask |= (1 << (pin - 1)) + self.layouts.append( (id, mask) ) + + def supportedLayouts(self): + """Returns a list of supported layouts. + Each entry is a tuple of (id, bitmask), where bitmask is + the ZIF layout. bit0 is ZIF-pin-1. A bit set means a hot pin.""" + return self.layouts + + def setLayoutPins(self, zifPinsList): + """Load a layout. zifPinsList is a list of hot ZIF pins. + The first ZIF pin is 1.""" + zifMask = 0 + for zifPin in zifPinsList: + assert(zifPin >= 1) + zifMask |= (1 << (zifPin - 1)) + return self.setLayoutMask(zifMask) + + def setLayoutMask(self, zifMask): + "Load a ZIF mask." + for (layoutId, layoutMask) in self.layouts: + if layoutMask == zifMask: + self.setLayoutID(layoutId) + return True + raise Exception() + #return False + + def setLayoutID(self, id): + "Load a specific layout ID." + self.top.cmdLoadGNDLayout(id) diff --git a/libtoprammer/top2049/shiftreg_layout.py b/libtoprammer/top2049/shiftreg_layout.py new file mode 100644 index 0000000..d5a06de --- /dev/null +++ b/libtoprammer/top2049/shiftreg_layout.py @@ -0,0 +1,98 @@ +""" +# TOP2049 Open Source programming suite +# +# TOP2049 Shiftregister based layout definitions +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +class ShiftregLayout: + def __init__(self, nrShiftRegs): + assert(nrShiftRegs <= 4) + self.nrShiftRegs = nrShiftRegs + self.layouts = [] + for id in range(0, len(self.shiftreg_masks)): + shreg_mask = self.shiftreg_masks[id] + zif_mask = 0 + for bit in range(0, self.nrShiftRegs * 8): + if (shreg_mask & (1 << bit)) == 0: + continue + regId = self.__bitnr2shregId(bit) + zifPin = self.shreg2zif_map[regId] + zif_mask |= (1 << (zifPin - 1)) + if id == 0 or zif_mask != 0: + self.layouts.append( (id, zif_mask) ) + + def __bitnr2shregId(self, bitNr): + if bitNr >= 24: + register = 3 + pin = bitNr - 24 + elif bitNr >= 16: + register = 2 + pin = bitNr - 16 + elif bitNr >= 8: + register = 1 + pin = bitNr - 8 + else: + register = 0 + pin = bitNr + return "%d.%d" % (register, pin) + + def __repr__(self): + res = "" + for (id, zif_mask) in self.supportedLayouts(): + res += "Layout %d:\n" % id + res += " o---------o\n" + for pin in range(1, 25): + left = " " + right = "" + if (1 << (pin - 1)) & zif_mask: + left = "HOT >" + if (1 << (49 - pin - 1)) & zif_mask: + right = "< HOT" + res += "%s | %2d | %2d | %s\n" % (left, pin, 49 - pin, right) + res += " o---------o\n\n" + return res + + def supportedLayouts(self): + """Returns a list of supported layouts. + Each entry is a tuple of (id, bitmask), where bitmask is + the ZIF layout. bit0 is ZIF-pin-1. A bit set means a hot pin.""" + return self.layouts + + def setLayoutPins(self, zifPinsList): + """Load a layout. zifPinsList is a list of hot ZIF pins. + The first ZIF pin is 1.""" + zifMask = 0 + for zifPin in zifPinsList: + assert(zifPin >= 1) + zifMask |= (1 << (zifPin - 1)) + return self.setLayoutMask(zifMask) + + def setLayoutMask(self, zifMask): + "Load a ZIF mask." + for (layoutId, layoutMask) in self.layouts: + if layoutMask == zifMask: + self.setLayoutID(layoutId) + return True + raise Exception() + #return False + + def setLayoutID(self, id): + "Load a specific layout ID." + # Reimplement me in the subclass + raise Exception() diff --git a/libtoprammer/top2049/vccx_layouts.py b/libtoprammer/top2049/vccx_layouts.py new file mode 100644 index 0000000..b1df094 --- /dev/null +++ b/libtoprammer/top2049/vccx_layouts.py @@ -0,0 +1,150 @@ +""" +# TOP2049 Open Source programming suite +# +# TOP2049 VCCX layout definitions +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from shiftreg_layout import * + +class VCCXLayout(ShiftregLayout): + # "shiftreg_masks" is a dump of the VCCX shiftregister states. The array index + # is the layout ID and the array entries are the inverted shift + # register outputs. The least significant byte is the first + # shift register in the chain. + shiftreg_masks = ( + 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + 0x000000, 0x000000, 0x000001, 0x000000, 0x000000, 0x002000, + 0x000000, 0x000002, 0x000000, 0x000000, 0x080000, 0x000004, + 0x000000, 0x000000, 0x010000, 0x004000, 0x000000, 0x000000, + 0x000008, 0x000010, 0x000020, 0x000040, 0x000080, 0x000000, + 0x000100, 0x000000, 0x000200, 0x000000, 0x000400, 0x000000, + 0x000800, 0x000000, 0x008000, 0x000000, 0x001000, 0x000000, + 0x020000, 0x000000, 0x040000, #0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x012000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, + #0x000000, 0x000000, 0x000000, 0x000000, + ) + # "shreg2zif_map" is a mapping of the shift register outputs + # to the ZIF socket pins + shreg2zif_map = { + # SHREG.PIN : ZIF_PIN + + # left side + # 1 + # 2 + # 3 + # 4 + # 5 + # 6 + # 7 + # 8 + # 9 + # 10 + # 11 + "0.0" : 12, # Q8C + # 13 + # 14 + "1.5" : 15, # Q11C + # 16 + "0.1" : 17, # Q13C + # 18 + # 19 + "2.3" : 20, # Q16C + "0.2" : 21, # Q17C + # 22 + # 23 + "2.0" : 24, # Q20C + + # right side + "2.2" : 48, # Q44C + # 47 + "2.1" : 46, # Q42C + # 45 + "1.4" : 44, # Q40C + # 43 + "1.7" : 42, # Q38C + # 41 + "1.3" : 40, # Q36C + # 39 + "1.2" : 38, # Q34C + # 37 + "1.1" : 36, # Q32C + # 35 + "1.0" : 34, # Q30C + # 33 + "0.7" : 32, # Q28C + "0.6" : 31, # Q27C + "0.5" : 30, # Q26C + "0.4" : 29, # Q25C + "0.3" : 28, # Q24C + # 27 + # 26 + "1.6" : 25, # Q21C + } + + def __init__(self, top): + ShiftregLayout.__init__(self, 3) + self.top = top + + def minVoltage(self): + "Get the min supported voltage" + return 3 + + def maxVoltage(self): + "Get the max supported voltage" + return 5 + + def setLayoutID(self, id): + self.top.cmdLoadVCCXLayout(id) + +if __name__ == "__main__": + print "ZIF socket VCCX layouts" + print VCCXLayout(None) diff --git a/libtoprammer/top2049/vpp_layouts.py b/libtoprammer/top2049/vpp_layouts.py new file mode 100644 index 0000000..07d5845 --- /dev/null +++ b/libtoprammer/top2049/vpp_layouts.py @@ -0,0 +1,159 @@ +""" +# TOP2049 Open Source programming suite +# +# TOP2049 VPP layout definitions +# +# Copyright (c) 2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +from shiftreg_layout import * + +class VPPLayout(ShiftregLayout): + # "shiftreg_masks" is a dump of the VPP shiftregister states. The array index + # is the layout ID and the array entries are the inverted shift + # register outputs. The least significant byte is the first + # shift register in the chain. + shiftreg_masks = ( + 0x00000000, 0x02000000, 0x03000000, 0x03000008, 0x03000008, + 0x03100008, 0x03100008, 0x03120008, 0x03130008, 0x03134008, + 0x03136008, 0x03137008, 0x03137208, 0x03137208, 0x03137308, + 0x03137328, 0x03137328, 0x03137328, 0x03137328, 0x03137328, + 0x03137329, 0x03137329, 0x0313732B, 0x0313732B, 0x0313732B, + 0x0313732B, 0x0313732F, 0x0313733F, 0x0313737F, 0x031373FF, + 0x031377FF, 0x03137FFF, 0x03137FFF, 0x0313FFFF, 0x0317FFFF, + 0x031FFFFF, 0x031FFFFF, 0x033FFFFF, 0x033FFFFF, 0x037FFFFF, + 0x03FFFFFF, 0x03FFFFFF, 0x07FFFFFF, 0x0FFFFFFF, 0x8FFFFFFF, + 0xCFFFFFFF, 0xEFFFFFFF, 0xFFFFFFFF, #0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + #0xFFFFFFFF, + ) + # "shreg2zif_map" is a mapping of the shift register outputs + # to the ZIF socket pins + shreg2zif_map = { + # SHREG.PIN : ZIF_PIN + + # left side + "3.6" : 1, # QP31 + "3.5" : 2, # QP30 + "3.4" : 3, # QP29 + # 4 + "3.1" : 5, # QP26 + "3.0" : 6, # QP25 + "0.3" : 7, # QP4 + # 8 + "2.4" : 9, # QP21 + # 10 + "2.1" : 11, # QP18 + "2.0" : 12, # QP17 + "1.6" : 13, # QP15 + "1.5" : 14, # QP14 + "1.4" : 15, # QP13 + "1.1" : 16, # QP10 + # 17 + "1.0" : 18, # QP9 + "0.5" : 19, # QP6 + # 20 + # 21 + # 22 + # 23 + "0.0" : 24, # QP1 + + # right side + "3.7" : 48, # QP32 + "3.3" : 47, # QP28 + "3.2" : 46, # QP27 + # 45 + "2.7" : 44, # QP24 + "2.6" : 43, # QP23 + # 42 + "2.5" : 41, # QP22 + # 40 + "2.3" : 39, # QP20 + "2.2" : 38, # QP19 + "1.7" : 37, # QP16 + # 36 + "1.3" : 35, # QP12 + "1.2" : 34, # QP11 + "0.7" : 33, # QP8 + "0.6" : 32, # QP7 + "0.4" : 31, # QP5 + "0.2" : 30, # QP3 + # 29 + # 28 + # 27 + "0.1" : 26, # QP2 + # 25 + } + + def __init__(self, top): + ShiftregLayout.__init__(self, 4) + self.top = top + + def minVoltage(self): + "Get the min supported voltage" + return 5 + + def maxVoltage(self): + "Get the max supported voltage" + return 21 + + def setLayoutID(self, id): + self.top.cmdLoadVPPLayout(id) + +if __name__ == "__main__": + print "ZIF socket VPP layouts" + print VPPLayout(None) diff --git a/libtoprammer/toprammer_main.py b/libtoprammer/toprammer_main.py new file mode 100644 index 0000000..f3c8278 --- /dev/null +++ b/libtoprammer/toprammer_main.py @@ -0,0 +1,436 @@ +""" +# TOP2049 Open Source programming suite +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +VERSION_MAJOR = 0 +VERSION_MINOR = 1 +VERSION = "%d.%d" % (VERSION_MAJOR, VERSION_MINOR) + +from bitfile import * +from util import * + +import sys +import time +try: + import usb +except (ImportError), e: + print "Python USB support module not found. Please install python-usb." + sys.exit(1) + +# TOP2049 specific stuff +import top2049.vccx_layouts +import top2049.vpp_layouts +import top2049.gnd_layouts + +# Import the supported chip modules +from chip_atmega32dip40 import * +from chip_atmega8dip28 import * +from chip_atmega88dip28 import * +from chip_m8cissp import * +from chip_m2764a import * +from chip_unitest import * + + +class TOP: + def __init__(self, bitfileName, busDev=None, verbose=0, + forceLevel=0, noqueue=False, usebroken=False): + """bitfileName is the path to the .bit file. + busDev is a tuple (BUSID, DEVID) or None.""" + + self.verbose = verbose + self.forceLevel = forceLevel + self.noqueue = noqueue + self.usebroken = usebroken + + self.commandQueue = [] + + self.bitfile = Bitfile() + self.bitfile.parseFile(bitfileName) + + # Find a chip handler for the given bitfile. + chipID = self.bitfile.getSrcFile().lower() + if chipID.endswith(".ncd"): + chipID = chipID[0:-4] + self.chip = chipFind(chipID) + if self.chip and self.chip.isBroken() and not usebroken: + self.chip = None + if not self.chip: + raise TOPException("Did not find an implementation for the chip %s" % chipID) + self.chip.setTOP(self) + + # Find the device + for bus in usb.busses(): + if busDev and bus.dirname != "%03d" % busDev[0]: + continue + for dev in bus.devices: + if busDev and dev.filename != "%03d" % busDev[1]: + continue + if self.__isTOP(dev): + break + if busDev: + raise TOPException( + "Device %03d.%03d is not a TOP device" %\ + (busDev[0], busDev[1])) + else: + continue + break + else: + raise TOPException("TOP programmer device not found!") + self.usbbus = bus + self.usbdev = dev + self.bulkOut = None + self.bulkIn = None + + # Set up the USB interface + try: + self.usbh = self.usbdev.open() + config = self.usbdev.configurations[0] + interface = config.interfaces[0][0] + + # Find the endpoints + for ep in interface.endpoints: + if not self.bulkIn and \ + ep.type == usb.ENDPOINT_TYPE_BULK and \ + (ep.address & usb.ENDPOINT_IN) != 0: + self.bulkIn = ep + if not self.bulkOut and \ + ep.type == usb.ENDPOINT_TYPE_BULK and \ + (ep.address & usb.ENDPOINT_IN) == 0: + self.bulkOut = ep + if not self.bulkIn or not self.bulkOut: + raise TOPException("Did not find all USB EPs") + + self.usbh.setConfiguration(config) + self.usbh.claimInterface(interface) + self.usbh.setAltInterface(interface) + self.usbh.clearHalt(self.bulkOut.address) + self.usbh.clearHalt(self.bulkIn.address) + except (usb.USBError), e: + raise TOPException("USB error: " + str(e)) + + if self.noqueue: + self.printWarning("WARNING: Command queuing disabled. " +\ + "Hardware access will be _really_ slow.") + + # For now we assume a TOP2049 + self.vccx = top2049.vccx_layouts.VCCXLayout(self) + self.vpp = top2049.vpp_layouts.VPPLayout(self) + self.gnd = top2049.gnd_layouts.GNDLayout(self) + + self.__initializeHardware() + + def shutdown(self): + self.chip.shutdownChip() + self.flushCommands() + + def getForceLevel(self): + return self.forceLevel + + def printWarning(self, message, newline=True): + if self.verbose >= 0: + self.flushCommands() + if newline: + print message + else: + sys.stdout.write(message) + sys.stdout.flush() + + def printInfo(self, message, newline=True): + if self.verbose >= 1: + self.flushCommands() + if newline: + print message + else: + sys.stdout.write(message) + sys.stdout.flush() + + def printDebug(self, message, newline=True): + if self.verbose >= 2: + self.flushCommands() + if newline: + print message + else: + sys.stdout.write(message) + sys.stdout.flush() + + @staticmethod + def __isTOP(usbdev): + ids = ( (0x2471, 0x0853), ) + return (usbdev.idVendor, usbdev.idProduct) in ids + + def __initializeHardware(self): + "Initialize the hardware" + ver = self.cmdRequestVersion() + self.printInfo("Initializing the '" + ver + "'...") + + self.queueCommand("\x0D") + stat = self.cmdReadStatusReg32() + if stat != 0x00020C69: + raise TOPException("Init: Unexpected status register (a): 0x%08X" % stat) + + self.cmdFPGAWrite(0x1B, 0xFF) + self.cmdSetVPPVoltage(0) + self.cmdSetVPPVoltage(0) + self.cmdSetVPPVoltage(0) + self.cmdSetVPPVoltage(12) + self.queueCommand("\x0E\x20\x00\x00") + self.cmdFlush() + self.cmdSetVCCXVoltage(0) + self.cmdFPGAWrite(0x1D, 0x86) + self.cmdLoadGNDLayout(0) + self.cmdLoadVPPLayout(0) + self.cmdLoadVCCXLayout(0) + self.cmdSetVPPVoltage(0) + self.cmdSetVPPVoltage(12) + self.queueCommand("\x0E\x20\x00\x00") + self.cmdFlush() + self.queueCommand("\x0E\x25\x00\x00") + stat = self.cmdReadStatusReg32() + if stat != 0x0000686C: + raise TOPException("Init: Unexpected status register (b): 0x%08X" % stat) + + self.__bitfileUpload() + self.chip.initializeChip() + + def __bitfileUpload(self): + self.printDebug("Uploading bitfile %s..." % self.bitfile.getFilename()) + + self.cmdFPGAWrite(0x1B, 0x00) + self.cmdFPGAInitiateConfig() + stat = self.cmdReadStatusReg32() + if stat != 0x00006801: + raise TOPException("bit-upload: Failed to initiate " +\ + "config sequence (0x%08X)" % stat) + + data = self.bitfile.getPayload() + for i in range(0, len(data), 60): + self.cmdFPGAUploadConfig(data[i : i + 60]) + self.flushCommands() + + def readSignature(self): + """Reads the device signature and returns it.""" + self.printDebug("Reading signature from chip...") + sig = self.chip.readSignature() + self.printDebug("Done reading %d bytes." % len(sig)) + return sig + + def eraseChip(self): + """Erase the chip.""" + self.printDebug("Erasing chip...") + self.chip.erase() + + def readProgmem(self): + """Reads the program memory image and returns it.""" + self.printDebug("Reading program memory from chip...") + image = self.chip.readProgmem() + self.printDebug("Done reading %d bytes." % len(image)) + return image + + def writeProgmem(self, image): + """Writes a program memory image to the chip.""" + self.printDebug("Writing %d bytes of program memory to chip..." % len(image)) + self.chip.writeProgmem(image) + self.printDebug("Done writing image.") + + def readEEPROM(self): + """Reads the EEPROM image and returns it.""" + self.printDebug("Reading EEPROM from chip...") + image = self.chip.readEEPROM() + self.printDebug("Done reading %d bytes." % len(image)) + return image + + def writeEEPROM(self, image): + """Writes an EEPROM image to the chip.""" + self.printDebug("Writing %d bytes of EEPROM to chip..." % len(image)) + self.chip.writeEEPROM(image) + self.printDebug("Done writing image.") + + def readFuse(self): + """Reads the fuses image and returns it.""" + self.printDebug("Reading fuses from chip...") + image = self.chip.readFuse() + self.printDebug("Done reading %d bytes." % len(image)) + return image + + def writeFuse(self, image): + """Writes a fuses image to the chip.""" + self.printDebug("Writing %d bytes of fuses to chip..." % len(image)) + self.chip.writeFuse(image) + self.printDebug("Done writing image.") + + def readLockbits(self): + """Reads the Lock bits image and returns it.""" + self.printDebug("Reading lock-bits from chip...") + image = self.chip.readLockbits() + self.printDebug("Done reading %d bytes." % len(image)) + return image + + def writeLockbits(self, image): + """Writes a Lock bits image to the chip.""" + self.printDebug("Writing %d bytes of lock-bits to chip..." % len(image)) + self.chip.writeLockbits(image) + self.printDebug("Done writing image.") + + def cmdFlush(self, count=1): + """Send 'count' flush requests.""" + assert(count >= 1) + self.flushCommands() + self.queueCommand(chr(0x1B) * count) + self.flushCommands() + + def cmdReadStatusReg(self): + """Read the status register. Returns 64 bytes.""" + self.queueCommand(chr(0x07)) + return self.receive(64) + + def cmdReadStatusReg32(self): + """Read a 32bit value from the status register.""" + stat = self.cmdReadStatusReg() + stat = ord(stat[0]) | (ord(stat[1]) << 8) | \ + (ord(stat[2]) << 16) | (ord(stat[3]) << 24) + return stat + + def cmdReadStatusReg48(self): + """Read a 48bit value from the status register.""" + stat = self.cmdReadStatusReg() + stat = ord(stat[0]) | (ord(stat[1]) << 8) | \ + (ord(stat[2]) << 16) | (ord(stat[3]) << 24) | \ + (ord(stat[4]) << 32) | (ord(stat[5]) << 40) + return stat + + def cmdRequestVersion(self): + """Returns the device ID and versioning string.""" + self.queueCommand("\x0E\x11\x00\x00") + data = self.cmdReadStatusReg() + return data[0:16].strip() + + def cmdFPGAInitiateConfig(self): + """Initiate a configuration sequence on the FPGA.""" + self.queueCommand("\x0E\x21\x00\x00") + + def cmdFPGAUploadConfig(self, data): + """Upload configuration data into the FPGA.""" + assert(len(data) <= 60) + cmd = "\x0E\x22\x00\x00" + data + cmd += "\x00" * (64 - len(cmd)) # padding + self.queueCommand(cmd) + + def cmdFPGAReadByte(self): + """Read a byte from the FPGA data line into the status register.""" + self.queueCommand("\x01") + + def cmdFPGAReadRaw(self, address): + """Read a byte from the FPGA at address into the status register.""" + cmd = chr(0x0B) + chr(address) + self.queueCommand(cmd) + + def cmdFPGAWrite(self, address, byte): + """Write a byte to an FPGA address.""" + cmd = chr(0x0A) + chr(address) + chr(byte) + self.queueCommand(cmd) + + def cmdLoadGNDLayout(self, layout): + """Load the GND configuration into the H/L shiftregisters.""" + cmd = chr(0x0E) + chr(0x16) + chr(layout) + chr(0) + self.queueCommand(cmd) + self.delay(0.15) + self.cmdFlush() + + def cmdSetVPPVoltage(self, voltage): + """Set the VPP voltage. voltage is a floating point voltage number.""" + centivolt = int(voltage * 10) + cmd = chr(0x0E) + chr(0x12) + chr(centivolt) + chr(0) + self.queueCommand(cmd) + self.cmdFlush() + + def cmdLoadVPPLayout(self, layout): + """Load the VPP configuration into the shift registers.""" + cmd = chr(0x0E) + chr(0x14) + chr(layout) + chr(0) + self.queueCommand(cmd) + self.delay(0.15) + self.cmdFlush() + + def cmdSetVCCXVoltage(self, voltage): + """Set the VCCX voltage. voltage is a floating point voltage number.""" + centivolt = int(voltage * 10) + cmd = chr(0x0E) + chr(0x13) + chr(centivolt) + chr(0) + self.queueCommand(cmd) + self.cmdFlush() + + def cmdLoadVCCXLayout(self, layout): + """Load the VCCX configuration into the shift registers.""" + cmd = chr(0x0E) + chr(0x15) + chr(layout) + chr(0) + self.queueCommand(cmd) + self.delay(0.15) + self.cmdFlush() + + def __doSend(self, command): + try: + assert(len(command) <= 64) + if self.verbose >= 3: + print "Sending command:" + dumpMem(command) + ep = self.bulkOut.address + self.usbh.bulkWrite(ep, command) + except (usb.USBError), e: + raise TOPException("USB bulk write error: " + str(e)) + + def queueCommand(self, command): + """Queue a raw command for transmission.""" + assert(len(command) <= 64) + if self.noqueue: + self.__doSend(command) + else: + self.commandQueue.append(command) + if len(self.commandQueue) >= 128: + self.flushCommands() + + def receive(self, size): + """Receive 'size' bytes on the bulk-in ep.""" + # If there are blocked commands in the queue, send them now. + self.flushCommands() + try: + ep = self.bulkIn.address + data = "" + for c in self.usbh.bulkRead(ep, size): + data += chr(c) + if self.verbose >= 3: + print "Received data:" + dumpMem(data) + except (usb.USBError), e: + raise TOPException("USB bulk read error: " + str(e)) + return data + + def flushCommands(self): + """Flush the command queue, but don't unblock it.""" + command = "" + for oneCommand in self.commandQueue: + assert(len(oneCommand) <= 64) + if len(command) + len(oneCommand) > 64: + self.__doSend(command) + command = "" + command += oneCommand + if command: + self.__doSend(command) + self.commandQueue = [] + + def delay(self, seconds): + """Flush all commands and delay for 'seconds'""" + self.flushCommands() + time.sleep(seconds) diff --git a/libtoprammer/util.py b/libtoprammer/util.py new file mode 100644 index 0000000..80afadf --- /dev/null +++ b/libtoprammer/util.py @@ -0,0 +1,75 @@ +""" +# TOP2049 Open Source programming suite +# +# Utility functions +# +# Copyright (c) 2009-2010 Michael Buesch +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +""" + +import sys +import re + + +class TOPException(Exception): pass + + +hexdump_re = re.compile(r"0x[0-9a-fA-F]+:\s+([0-9a-fA-F\s]+)\s+.+") + +def parseHexdump(dump): + try: + bin = [] + for line in dump.splitlines(): + line = line.strip() + if not line: + continue + m = hexdump_re.match(line) + if not m: + raise TOPException("Invalid hexdump format (regex failure)") + bytes = m.group(1).replace(" ", "") + if len(bytes) % 2 != 0: + raise TOPException("Invalid hexdump format (odd bytestring len)") + for i in range(0, len(bytes), 2): + byte = int(bytes[i:i+2], 16) + bin.append(chr(byte)) + return "".join(bin) + except (ValueError), e: + raise TOPException("Invalid hexdump format (Integer error)") + +def generateHexdump(mem): + def toAscii(char): + if char >= 32 and char <= 126: + return chr(char) + return "." + + ret = "" + ascii = "" + for i in range(0, len(mem)): + if i % 16 == 0 and i != 0: + ret += " " + ascii + "\n" + ascii = "" + if i % 16 == 0: + ret += "0x%04X: " % i + c = ord(mem[i]) + ret += "%02X" % c + if (i % 2 != 0): + ret += " " + ascii += toAscii(c) + ret += " " + ascii + "\n\n" + return ret + +def dumpMem(mem): + sys.stdout.write(generateHexdump(mem)) diff --git a/makerelease.sh b/makerelease.sh index 53baef6..6a8d55e 100755 --- a/makerelease.sh +++ b/makerelease.sh @@ -4,9 +4,10 @@ set -e project="toprammer" -origin="$(pwd)" -version_major="$(cat $origin/toprammer | grep -e VERSION_MAJOR | head -n1 | cut -d'=' -f2)" -version_minor="$(cat $origin/toprammer | grep -e VERSION_MINOR | head -n1 | cut -d'=' -f2)" +origin="$PWD/$(dirname $0)" + +version_major="$(cat $origin/libtoprammer/toprammer_main.py | grep -e VERSION_MAJOR | head -n1 | cut -d'=' -f2)" +version_minor="$(cat $origin/libtoprammer/toprammer_main.py | grep -e VERSION_MINOR | head -n1 | cut -d'=' -f2)" version="$(printf %d.%d $version_major $version_minor)" if [ -z "$version" ]; then echo "Could not determine version!" diff --git a/setup.py b/setup.py new file mode 100755 index 0000000..8f2680a --- /dev/null +++ b/setup.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python + +from distutils.core import setup +import libtoprammer.toprammer_main as toprammer_main + +setup( name = "toprammer", + version = toprammer_main.VERSION, + description = "TOP2049 Open Source programming suite", + author = "Michael Buesch", + author_email = "mb@bu3sch.de", + url = "http://bu3sch.de/joomla/index.php/toprammer-top2049", + packages = [ "libtoprammer", "libtoprammer/top2049", ], + package_data = { "libtoprammer" : [ "bit/*.bit" ], }, + scripts = [ "toprammer", "toprammer-unitest", ], +) diff --git a/top2049/__init__.py b/top2049/__init__.py deleted file mode 100644 index 8d1c8b6..0000000 --- a/top2049/__init__.py +++ /dev/null @@ -1 +0,0 @@ - diff --git a/top2049/gnd_layouts.py b/top2049/gnd_layouts.py deleted file mode 100644 index 4e48688..0000000 --- a/top2049/gnd_layouts.py +++ /dev/null @@ -1,66 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# TOP2049 GND layout definitions -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -class GNDLayout: - # A list of valid ZIF GND pins (0=none) - validPins = (0, 5, 14, 15, 16, 17, 18, 19, 20, 24, 26, 27, - 28, 29, 33, 34, 35) - - def __init__(self, top): - self.top = top - self.layouts = [] - for pin in self.validPins: - id = pin - if id != 0: - id -= 4 - mask = 0 - if pin != 0: - mask |= (1 << (pin - 1)) - self.layouts.append( (id, mask) ) - - def supportedLayouts(self): - """Returns a list of supported layouts. - Each entry is a tuple of (id, bitmask), where bitmask is - the ZIF layout. bit0 is ZIF-pin-1. A bit set means a hot pin.""" - return self.layouts - - def setLayoutPins(self, zifPinsList): - """Load a layout. zifPinsList is a list of hot ZIF pins. - The first ZIF pin is 1.""" - zifMask = 0 - for zifPin in zifPinsList: - assert(zifPin >= 1) - zifMask |= (1 << (zifPin - 1)) - return self.setLayoutMask(zifMask) - - def setLayoutMask(self, zifMask): - "Load a ZIF mask." - for (layoutId, layoutMask) in self.layouts: - if layoutMask == zifMask: - self.setLayoutID(layoutId) - return True - raise Exception() - #return False - - def setLayoutID(self, id): - "Load a specific layout ID." - self.top.cmdLoadGNDLayout(id) diff --git a/top2049/shiftreg_layout.py b/top2049/shiftreg_layout.py deleted file mode 100644 index d5a06de..0000000 --- a/top2049/shiftreg_layout.py +++ /dev/null @@ -1,98 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# TOP2049 Shiftregister based layout definitions -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -class ShiftregLayout: - def __init__(self, nrShiftRegs): - assert(nrShiftRegs <= 4) - self.nrShiftRegs = nrShiftRegs - self.layouts = [] - for id in range(0, len(self.shiftreg_masks)): - shreg_mask = self.shiftreg_masks[id] - zif_mask = 0 - for bit in range(0, self.nrShiftRegs * 8): - if (shreg_mask & (1 << bit)) == 0: - continue - regId = self.__bitnr2shregId(bit) - zifPin = self.shreg2zif_map[regId] - zif_mask |= (1 << (zifPin - 1)) - if id == 0 or zif_mask != 0: - self.layouts.append( (id, zif_mask) ) - - def __bitnr2shregId(self, bitNr): - if bitNr >= 24: - register = 3 - pin = bitNr - 24 - elif bitNr >= 16: - register = 2 - pin = bitNr - 16 - elif bitNr >= 8: - register = 1 - pin = bitNr - 8 - else: - register = 0 - pin = bitNr - return "%d.%d" % (register, pin) - - def __repr__(self): - res = "" - for (id, zif_mask) in self.supportedLayouts(): - res += "Layout %d:\n" % id - res += " o---------o\n" - for pin in range(1, 25): - left = " " - right = "" - if (1 << (pin - 1)) & zif_mask: - left = "HOT >" - if (1 << (49 - pin - 1)) & zif_mask: - right = "< HOT" - res += "%s | %2d | %2d | %s\n" % (left, pin, 49 - pin, right) - res += " o---------o\n\n" - return res - - def supportedLayouts(self): - """Returns a list of supported layouts. - Each entry is a tuple of (id, bitmask), where bitmask is - the ZIF layout. bit0 is ZIF-pin-1. A bit set means a hot pin.""" - return self.layouts - - def setLayoutPins(self, zifPinsList): - """Load a layout. zifPinsList is a list of hot ZIF pins. - The first ZIF pin is 1.""" - zifMask = 0 - for zifPin in zifPinsList: - assert(zifPin >= 1) - zifMask |= (1 << (zifPin - 1)) - return self.setLayoutMask(zifMask) - - def setLayoutMask(self, zifMask): - "Load a ZIF mask." - for (layoutId, layoutMask) in self.layouts: - if layoutMask == zifMask: - self.setLayoutID(layoutId) - return True - raise Exception() - #return False - - def setLayoutID(self, id): - "Load a specific layout ID." - # Reimplement me in the subclass - raise Exception() diff --git a/top2049/vccx_layouts.py b/top2049/vccx_layouts.py deleted file mode 100644 index b1df094..0000000 --- a/top2049/vccx_layouts.py +++ /dev/null @@ -1,150 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# TOP2049 VCCX layout definitions -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from shiftreg_layout import * - -class VCCXLayout(ShiftregLayout): - # "shiftreg_masks" is a dump of the VCCX shiftregister states. The array index - # is the layout ID and the array entries are the inverted shift - # register outputs. The least significant byte is the first - # shift register in the chain. - shiftreg_masks = ( - 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - 0x000000, 0x000000, 0x000001, 0x000000, 0x000000, 0x002000, - 0x000000, 0x000002, 0x000000, 0x000000, 0x080000, 0x000004, - 0x000000, 0x000000, 0x010000, 0x004000, 0x000000, 0x000000, - 0x000008, 0x000010, 0x000020, 0x000040, 0x000080, 0x000000, - 0x000100, 0x000000, 0x000200, 0x000000, 0x000400, 0x000000, - 0x000800, 0x000000, 0x008000, 0x000000, 0x001000, 0x000000, - 0x020000, 0x000000, 0x040000, #0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x012000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000, - #0x000000, 0x000000, 0x000000, 0x000000, - ) - # "shreg2zif_map" is a mapping of the shift register outputs - # to the ZIF socket pins - shreg2zif_map = { - # SHREG.PIN : ZIF_PIN - - # left side - # 1 - # 2 - # 3 - # 4 - # 5 - # 6 - # 7 - # 8 - # 9 - # 10 - # 11 - "0.0" : 12, # Q8C - # 13 - # 14 - "1.5" : 15, # Q11C - # 16 - "0.1" : 17, # Q13C - # 18 - # 19 - "2.3" : 20, # Q16C - "0.2" : 21, # Q17C - # 22 - # 23 - "2.0" : 24, # Q20C - - # right side - "2.2" : 48, # Q44C - # 47 - "2.1" : 46, # Q42C - # 45 - "1.4" : 44, # Q40C - # 43 - "1.7" : 42, # Q38C - # 41 - "1.3" : 40, # Q36C - # 39 - "1.2" : 38, # Q34C - # 37 - "1.1" : 36, # Q32C - # 35 - "1.0" : 34, # Q30C - # 33 - "0.7" : 32, # Q28C - "0.6" : 31, # Q27C - "0.5" : 30, # Q26C - "0.4" : 29, # Q25C - "0.3" : 28, # Q24C - # 27 - # 26 - "1.6" : 25, # Q21C - } - - def __init__(self, top): - ShiftregLayout.__init__(self, 3) - self.top = top - - def minVoltage(self): - "Get the min supported voltage" - return 3 - - def maxVoltage(self): - "Get the max supported voltage" - return 5 - - def setLayoutID(self, id): - self.top.cmdLoadVCCXLayout(id) - -if __name__ == "__main__": - print "ZIF socket VCCX layouts" - print VCCXLayout(None) diff --git a/top2049/vpp_layouts.py b/top2049/vpp_layouts.py deleted file mode 100644 index 07d5845..0000000 --- a/top2049/vpp_layouts.py +++ /dev/null @@ -1,159 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# TOP2049 VPP layout definitions -# -# Copyright (c) 2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -from shiftreg_layout import * - -class VPPLayout(ShiftregLayout): - # "shiftreg_masks" is a dump of the VPP shiftregister states. The array index - # is the layout ID and the array entries are the inverted shift - # register outputs. The least significant byte is the first - # shift register in the chain. - shiftreg_masks = ( - 0x00000000, 0x02000000, 0x03000000, 0x03000008, 0x03000008, - 0x03100008, 0x03100008, 0x03120008, 0x03130008, 0x03134008, - 0x03136008, 0x03137008, 0x03137208, 0x03137208, 0x03137308, - 0x03137328, 0x03137328, 0x03137328, 0x03137328, 0x03137328, - 0x03137329, 0x03137329, 0x0313732B, 0x0313732B, 0x0313732B, - 0x0313732B, 0x0313732F, 0x0313733F, 0x0313737F, 0x031373FF, - 0x031377FF, 0x03137FFF, 0x03137FFF, 0x0313FFFF, 0x0317FFFF, - 0x031FFFFF, 0x031FFFFF, 0x033FFFFF, 0x033FFFFF, 0x037FFFFF, - 0x03FFFFFF, 0x03FFFFFF, 0x07FFFFFF, 0x0FFFFFFF, 0x8FFFFFFF, - 0xCFFFFFFF, 0xEFFFFFFF, 0xFFFFFFFF, #0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, - #0xFFFFFFFF, - ) - # "shreg2zif_map" is a mapping of the shift register outputs - # to the ZIF socket pins - shreg2zif_map = { - # SHREG.PIN : ZIF_PIN - - # left side - "3.6" : 1, # QP31 - "3.5" : 2, # QP30 - "3.4" : 3, # QP29 - # 4 - "3.1" : 5, # QP26 - "3.0" : 6, # QP25 - "0.3" : 7, # QP4 - # 8 - "2.4" : 9, # QP21 - # 10 - "2.1" : 11, # QP18 - "2.0" : 12, # QP17 - "1.6" : 13, # QP15 - "1.5" : 14, # QP14 - "1.4" : 15, # QP13 - "1.1" : 16, # QP10 - # 17 - "1.0" : 18, # QP9 - "0.5" : 19, # QP6 - # 20 - # 21 - # 22 - # 23 - "0.0" : 24, # QP1 - - # right side - "3.7" : 48, # QP32 - "3.3" : 47, # QP28 - "3.2" : 46, # QP27 - # 45 - "2.7" : 44, # QP24 - "2.6" : 43, # QP23 - # 42 - "2.5" : 41, # QP22 - # 40 - "2.3" : 39, # QP20 - "2.2" : 38, # QP19 - "1.7" : 37, # QP16 - # 36 - "1.3" : 35, # QP12 - "1.2" : 34, # QP11 - "0.7" : 33, # QP8 - "0.6" : 32, # QP7 - "0.4" : 31, # QP5 - "0.2" : 30, # QP3 - # 29 - # 28 - # 27 - "0.1" : 26, # QP2 - # 25 - } - - def __init__(self, top): - ShiftregLayout.__init__(self, 4) - self.top = top - - def minVoltage(self): - "Get the min supported voltage" - return 5 - - def maxVoltage(self): - "Get the max supported voltage" - return 21 - - def setLayoutID(self, id): - self.top.cmdLoadVPPLayout(id) - -if __name__ == "__main__": - print "ZIF socket VPP layouts" - print VPPLayout(None) diff --git a/toprammer b/toprammer index 5142dec..e13c5c9 100755 --- a/toprammer +++ b/toprammer @@ -21,7 +21,7 @@ # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. """ -from toprammer_main import * +from libtoprammer.toprammer_main import * import getopt diff --git a/toprammer-unitest b/toprammer-unitest index f9453f2..b7803a5 100755 --- a/toprammer-unitest +++ b/toprammer-unitest @@ -21,7 +21,7 @@ # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. """ -from toprammer_main import * +from libtoprammer.toprammer_main import * from PyQt4.QtCore import * from PyQt4.QtGui import * diff --git a/toprammer_main.py b/toprammer_main.py deleted file mode 100644 index f3c8278..0000000 --- a/toprammer_main.py +++ /dev/null @@ -1,436 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -VERSION_MAJOR = 0 -VERSION_MINOR = 1 -VERSION = "%d.%d" % (VERSION_MAJOR, VERSION_MINOR) - -from bitfile import * -from util import * - -import sys -import time -try: - import usb -except (ImportError), e: - print "Python USB support module not found. Please install python-usb." - sys.exit(1) - -# TOP2049 specific stuff -import top2049.vccx_layouts -import top2049.vpp_layouts -import top2049.gnd_layouts - -# Import the supported chip modules -from chip_atmega32dip40 import * -from chip_atmega8dip28 import * -from chip_atmega88dip28 import * -from chip_m8cissp import * -from chip_m2764a import * -from chip_unitest import * - - -class TOP: - def __init__(self, bitfileName, busDev=None, verbose=0, - forceLevel=0, noqueue=False, usebroken=False): - """bitfileName is the path to the .bit file. - busDev is a tuple (BUSID, DEVID) or None.""" - - self.verbose = verbose - self.forceLevel = forceLevel - self.noqueue = noqueue - self.usebroken = usebroken - - self.commandQueue = [] - - self.bitfile = Bitfile() - self.bitfile.parseFile(bitfileName) - - # Find a chip handler for the given bitfile. - chipID = self.bitfile.getSrcFile().lower() - if chipID.endswith(".ncd"): - chipID = chipID[0:-4] - self.chip = chipFind(chipID) - if self.chip and self.chip.isBroken() and not usebroken: - self.chip = None - if not self.chip: - raise TOPException("Did not find an implementation for the chip %s" % chipID) - self.chip.setTOP(self) - - # Find the device - for bus in usb.busses(): - if busDev and bus.dirname != "%03d" % busDev[0]: - continue - for dev in bus.devices: - if busDev and dev.filename != "%03d" % busDev[1]: - continue - if self.__isTOP(dev): - break - if busDev: - raise TOPException( - "Device %03d.%03d is not a TOP device" %\ - (busDev[0], busDev[1])) - else: - continue - break - else: - raise TOPException("TOP programmer device not found!") - self.usbbus = bus - self.usbdev = dev - self.bulkOut = None - self.bulkIn = None - - # Set up the USB interface - try: - self.usbh = self.usbdev.open() - config = self.usbdev.configurations[0] - interface = config.interfaces[0][0] - - # Find the endpoints - for ep in interface.endpoints: - if not self.bulkIn and \ - ep.type == usb.ENDPOINT_TYPE_BULK and \ - (ep.address & usb.ENDPOINT_IN) != 0: - self.bulkIn = ep - if not self.bulkOut and \ - ep.type == usb.ENDPOINT_TYPE_BULK and \ - (ep.address & usb.ENDPOINT_IN) == 0: - self.bulkOut = ep - if not self.bulkIn or not self.bulkOut: - raise TOPException("Did not find all USB EPs") - - self.usbh.setConfiguration(config) - self.usbh.claimInterface(interface) - self.usbh.setAltInterface(interface) - self.usbh.clearHalt(self.bulkOut.address) - self.usbh.clearHalt(self.bulkIn.address) - except (usb.USBError), e: - raise TOPException("USB error: " + str(e)) - - if self.noqueue: - self.printWarning("WARNING: Command queuing disabled. " +\ - "Hardware access will be _really_ slow.") - - # For now we assume a TOP2049 - self.vccx = top2049.vccx_layouts.VCCXLayout(self) - self.vpp = top2049.vpp_layouts.VPPLayout(self) - self.gnd = top2049.gnd_layouts.GNDLayout(self) - - self.__initializeHardware() - - def shutdown(self): - self.chip.shutdownChip() - self.flushCommands() - - def getForceLevel(self): - return self.forceLevel - - def printWarning(self, message, newline=True): - if self.verbose >= 0: - self.flushCommands() - if newline: - print message - else: - sys.stdout.write(message) - sys.stdout.flush() - - def printInfo(self, message, newline=True): - if self.verbose >= 1: - self.flushCommands() - if newline: - print message - else: - sys.stdout.write(message) - sys.stdout.flush() - - def printDebug(self, message, newline=True): - if self.verbose >= 2: - self.flushCommands() - if newline: - print message - else: - sys.stdout.write(message) - sys.stdout.flush() - - @staticmethod - def __isTOP(usbdev): - ids = ( (0x2471, 0x0853), ) - return (usbdev.idVendor, usbdev.idProduct) in ids - - def __initializeHardware(self): - "Initialize the hardware" - ver = self.cmdRequestVersion() - self.printInfo("Initializing the '" + ver + "'...") - - self.queueCommand("\x0D") - stat = self.cmdReadStatusReg32() - if stat != 0x00020C69: - raise TOPException("Init: Unexpected status register (a): 0x%08X" % stat) - - self.cmdFPGAWrite(0x1B, 0xFF) - self.cmdSetVPPVoltage(0) - self.cmdSetVPPVoltage(0) - self.cmdSetVPPVoltage(0) - self.cmdSetVPPVoltage(12) - self.queueCommand("\x0E\x20\x00\x00") - self.cmdFlush() - self.cmdSetVCCXVoltage(0) - self.cmdFPGAWrite(0x1D, 0x86) - self.cmdLoadGNDLayout(0) - self.cmdLoadVPPLayout(0) - self.cmdLoadVCCXLayout(0) - self.cmdSetVPPVoltage(0) - self.cmdSetVPPVoltage(12) - self.queueCommand("\x0E\x20\x00\x00") - self.cmdFlush() - self.queueCommand("\x0E\x25\x00\x00") - stat = self.cmdReadStatusReg32() - if stat != 0x0000686C: - raise TOPException("Init: Unexpected status register (b): 0x%08X" % stat) - - self.__bitfileUpload() - self.chip.initializeChip() - - def __bitfileUpload(self): - self.printDebug("Uploading bitfile %s..." % self.bitfile.getFilename()) - - self.cmdFPGAWrite(0x1B, 0x00) - self.cmdFPGAInitiateConfig() - stat = self.cmdReadStatusReg32() - if stat != 0x00006801: - raise TOPException("bit-upload: Failed to initiate " +\ - "config sequence (0x%08X)" % stat) - - data = self.bitfile.getPayload() - for i in range(0, len(data), 60): - self.cmdFPGAUploadConfig(data[i : i + 60]) - self.flushCommands() - - def readSignature(self): - """Reads the device signature and returns it.""" - self.printDebug("Reading signature from chip...") - sig = self.chip.readSignature() - self.printDebug("Done reading %d bytes." % len(sig)) - return sig - - def eraseChip(self): - """Erase the chip.""" - self.printDebug("Erasing chip...") - self.chip.erase() - - def readProgmem(self): - """Reads the program memory image and returns it.""" - self.printDebug("Reading program memory from chip...") - image = self.chip.readProgmem() - self.printDebug("Done reading %d bytes." % len(image)) - return image - - def writeProgmem(self, image): - """Writes a program memory image to the chip.""" - self.printDebug("Writing %d bytes of program memory to chip..." % len(image)) - self.chip.writeProgmem(image) - self.printDebug("Done writing image.") - - def readEEPROM(self): - """Reads the EEPROM image and returns it.""" - self.printDebug("Reading EEPROM from chip...") - image = self.chip.readEEPROM() - self.printDebug("Done reading %d bytes." % len(image)) - return image - - def writeEEPROM(self, image): - """Writes an EEPROM image to the chip.""" - self.printDebug("Writing %d bytes of EEPROM to chip..." % len(image)) - self.chip.writeEEPROM(image) - self.printDebug("Done writing image.") - - def readFuse(self): - """Reads the fuses image and returns it.""" - self.printDebug("Reading fuses from chip...") - image = self.chip.readFuse() - self.printDebug("Done reading %d bytes." % len(image)) - return image - - def writeFuse(self, image): - """Writes a fuses image to the chip.""" - self.printDebug("Writing %d bytes of fuses to chip..." % len(image)) - self.chip.writeFuse(image) - self.printDebug("Done writing image.") - - def readLockbits(self): - """Reads the Lock bits image and returns it.""" - self.printDebug("Reading lock-bits from chip...") - image = self.chip.readLockbits() - self.printDebug("Done reading %d bytes." % len(image)) - return image - - def writeLockbits(self, image): - """Writes a Lock bits image to the chip.""" - self.printDebug("Writing %d bytes of lock-bits to chip..." % len(image)) - self.chip.writeLockbits(image) - self.printDebug("Done writing image.") - - def cmdFlush(self, count=1): - """Send 'count' flush requests.""" - assert(count >= 1) - self.flushCommands() - self.queueCommand(chr(0x1B) * count) - self.flushCommands() - - def cmdReadStatusReg(self): - """Read the status register. Returns 64 bytes.""" - self.queueCommand(chr(0x07)) - return self.receive(64) - - def cmdReadStatusReg32(self): - """Read a 32bit value from the status register.""" - stat = self.cmdReadStatusReg() - stat = ord(stat[0]) | (ord(stat[1]) << 8) | \ - (ord(stat[2]) << 16) | (ord(stat[3]) << 24) - return stat - - def cmdReadStatusReg48(self): - """Read a 48bit value from the status register.""" - stat = self.cmdReadStatusReg() - stat = ord(stat[0]) | (ord(stat[1]) << 8) | \ - (ord(stat[2]) << 16) | (ord(stat[3]) << 24) | \ - (ord(stat[4]) << 32) | (ord(stat[5]) << 40) - return stat - - def cmdRequestVersion(self): - """Returns the device ID and versioning string.""" - self.queueCommand("\x0E\x11\x00\x00") - data = self.cmdReadStatusReg() - return data[0:16].strip() - - def cmdFPGAInitiateConfig(self): - """Initiate a configuration sequence on the FPGA.""" - self.queueCommand("\x0E\x21\x00\x00") - - def cmdFPGAUploadConfig(self, data): - """Upload configuration data into the FPGA.""" - assert(len(data) <= 60) - cmd = "\x0E\x22\x00\x00" + data - cmd += "\x00" * (64 - len(cmd)) # padding - self.queueCommand(cmd) - - def cmdFPGAReadByte(self): - """Read a byte from the FPGA data line into the status register.""" - self.queueCommand("\x01") - - def cmdFPGAReadRaw(self, address): - """Read a byte from the FPGA at address into the status register.""" - cmd = chr(0x0B) + chr(address) - self.queueCommand(cmd) - - def cmdFPGAWrite(self, address, byte): - """Write a byte to an FPGA address.""" - cmd = chr(0x0A) + chr(address) + chr(byte) - self.queueCommand(cmd) - - def cmdLoadGNDLayout(self, layout): - """Load the GND configuration into the H/L shiftregisters.""" - cmd = chr(0x0E) + chr(0x16) + chr(layout) + chr(0) - self.queueCommand(cmd) - self.delay(0.15) - self.cmdFlush() - - def cmdSetVPPVoltage(self, voltage): - """Set the VPP voltage. voltage is a floating point voltage number.""" - centivolt = int(voltage * 10) - cmd = chr(0x0E) + chr(0x12) + chr(centivolt) + chr(0) - self.queueCommand(cmd) - self.cmdFlush() - - def cmdLoadVPPLayout(self, layout): - """Load the VPP configuration into the shift registers.""" - cmd = chr(0x0E) + chr(0x14) + chr(layout) + chr(0) - self.queueCommand(cmd) - self.delay(0.15) - self.cmdFlush() - - def cmdSetVCCXVoltage(self, voltage): - """Set the VCCX voltage. voltage is a floating point voltage number.""" - centivolt = int(voltage * 10) - cmd = chr(0x0E) + chr(0x13) + chr(centivolt) + chr(0) - self.queueCommand(cmd) - self.cmdFlush() - - def cmdLoadVCCXLayout(self, layout): - """Load the VCCX configuration into the shift registers.""" - cmd = chr(0x0E) + chr(0x15) + chr(layout) + chr(0) - self.queueCommand(cmd) - self.delay(0.15) - self.cmdFlush() - - def __doSend(self, command): - try: - assert(len(command) <= 64) - if self.verbose >= 3: - print "Sending command:" - dumpMem(command) - ep = self.bulkOut.address - self.usbh.bulkWrite(ep, command) - except (usb.USBError), e: - raise TOPException("USB bulk write error: " + str(e)) - - def queueCommand(self, command): - """Queue a raw command for transmission.""" - assert(len(command) <= 64) - if self.noqueue: - self.__doSend(command) - else: - self.commandQueue.append(command) - if len(self.commandQueue) >= 128: - self.flushCommands() - - def receive(self, size): - """Receive 'size' bytes on the bulk-in ep.""" - # If there are blocked commands in the queue, send them now. - self.flushCommands() - try: - ep = self.bulkIn.address - data = "" - for c in self.usbh.bulkRead(ep, size): - data += chr(c) - if self.verbose >= 3: - print "Received data:" - dumpMem(data) - except (usb.USBError), e: - raise TOPException("USB bulk read error: " + str(e)) - return data - - def flushCommands(self): - """Flush the command queue, but don't unblock it.""" - command = "" - for oneCommand in self.commandQueue: - assert(len(oneCommand) <= 64) - if len(command) + len(oneCommand) > 64: - self.__doSend(command) - command = "" - command += oneCommand - if command: - self.__doSend(command) - self.commandQueue = [] - - def delay(self, seconds): - """Flush all commands and delay for 'seconds'""" - self.flushCommands() - time.sleep(seconds) diff --git a/util.py b/util.py deleted file mode 100644 index 80afadf..0000000 --- a/util.py +++ /dev/null @@ -1,75 +0,0 @@ -""" -# TOP2049 Open Source programming suite -# -# Utility functions -# -# Copyright (c) 2009-2010 Michael Buesch -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -""" - -import sys -import re - - -class TOPException(Exception): pass - - -hexdump_re = re.compile(r"0x[0-9a-fA-F]+:\s+([0-9a-fA-F\s]+)\s+.+") - -def parseHexdump(dump): - try: - bin = [] - for line in dump.splitlines(): - line = line.strip() - if not line: - continue - m = hexdump_re.match(line) - if not m: - raise TOPException("Invalid hexdump format (regex failure)") - bytes = m.group(1).replace(" ", "") - if len(bytes) % 2 != 0: - raise TOPException("Invalid hexdump format (odd bytestring len)") - for i in range(0, len(bytes), 2): - byte = int(bytes[i:i+2], 16) - bin.append(chr(byte)) - return "".join(bin) - except (ValueError), e: - raise TOPException("Invalid hexdump format (Integer error)") - -def generateHexdump(mem): - def toAscii(char): - if char >= 32 and char <= 126: - return chr(char) - return "." - - ret = "" - ascii = "" - for i in range(0, len(mem)): - if i % 16 == 0 and i != 0: - ret += " " + ascii + "\n" - ascii = "" - if i % 16 == 0: - ret += "0x%04X: " % i - c = ord(mem[i]) - ret += "%02X" % c - if (i % 2 != 0): - ret += " " - ascii += toAscii(c) - ret += " " + ascii + "\n\n" - return ret - -def dumpMem(mem): - sys.stdout.write(generateHexdump(mem)) -- cgit v1.2.3