From 031078d37a6bc5b21c7ff5b16c972b2deb77a5ba Mon Sep 17 00:00:00 2001 From: Michael Buesch Date: Sat, 7 Apr 2012 00:03:34 +0200 Subject: Rename libtoprammer/bit to libtoprammer/fpga Signed-off-by: Michael Buesch --- README-DEVELOPERS.lyx | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'README-DEVELOPERS.lyx') diff --git a/README-DEVELOPERS.lyx b/README-DEVELOPERS.lyx index b86b675..4ee393a 100644 --- a/README-DEVELOPERS.lyx +++ b/README-DEVELOPERS.lyx @@ -658,7 +658,7 @@ http://www.xilinx.com/support/download/index.htm \begin_layout Standard To create a new sourcecode template fileset for a new chip, go to the libtopramm -er/bit/src/ subdirectory and execute the "create.sh" script: +er/fpga/src/ subdirectory and execute the "create.sh" script: \end_layout \begin_layout LyX-Code @@ -668,9 +668,9 @@ er/bit/src/ subdirectory and execute the "create.sh" script: \begin_layout Standard Where "bitfile_name" is the name of the new chip's bitfile. (That often matches the chip-ID). - Now go to libtoprammer/bit/src/bitfile_name/ and implement the bottom-half + Now go to libtoprammer/fpga/src/bitfile_name/ and implement the bottom-half algorithm in the bitfile_name.v Verilog file. - To build the .BIT file from the Verilog sources, go to the libtoprammer/bit/ + To build the .BIT file from the Verilog sources, go to the libtoprammer/fpga/ directory and execute: \end_layout -- cgit v1.2.3