From d9c63a6d622a408ea6115358d7f5e9506ce5eff5 Mon Sep 17 00:00:00 2001
From: Michael Buesch <mb@bu3sch.de>
Date: Wed, 27 Jan 2010 21:07:50 +0100
Subject: Some cleanups

Signed-off-by: Michael Buesch <mb@bu3sch.de>
---
 reverse-engineering/HWPROTOCOL             |  42 ++
 reverse-engineering/schematics/top2049.pro |   6 +
 reverse-engineering/schematics/top2049.sch | 748 +++++++++++++++++++++++++++++
 reverse-engineering/vccx_layouts_dump      | 135 ++++++
 reverse-engineering/vpp_layouts_dump       | 144 ++++++
 reverse-engineering/zif_connections.ods    | Bin 0 -> 17952 bytes
 6 files changed, 1075 insertions(+)
 create mode 100644 reverse-engineering/HWPROTOCOL
 create mode 100644 reverse-engineering/schematics/top2049.pro
 create mode 100644 reverse-engineering/schematics/top2049.sch
 create mode 100755 reverse-engineering/vccx_layouts_dump
 create mode 100755 reverse-engineering/vpp_layouts_dump
 create mode 100644 reverse-engineering/zif_connections.ods

(limited to 'reverse-engineering')

diff --git a/reverse-engineering/HWPROTOCOL b/reverse-engineering/HWPROTOCOL
new file mode 100644
index 0000000..36db583
--- /dev/null
+++ b/reverse-engineering/HWPROTOCOL
@@ -0,0 +1,42 @@
+TOP2049 USB protocol (incomplete)
+
+
+
+=== COMMANDS ===
+
+07		>= Read the status register.
+		   The register is read by sending 07h via bulk out
+		   and reading 64bytes via bulk in.
+
+0E110000	>= Put the device ID string into the status register.
+		   String length is 16 bytes.
+
+0E12xx00	>= Set VPP, where xx is the voltage.
+		   xx is in centivolt.
+
+0E13xx00	>= Set VCCX, where xx is the voltage.
+		   xx is in centivolt.
+
+0E14xx00	>= Load the ZIF socket VPP supply layout.
+		   xx is the layout ID.
+		   (Shift data into the 4 shiftregisters on the left side.
+		    Sends 4 times 8 clock pulses and one strobe.)
+
+0E15xx00	>= Load the ZIF socket VCCX supply layout.
+		   xx is the layout ID.
+		   (Shift data into the 3 shiftregisters on the right side.
+		    Sends 3 times 8 clock pulses and one strobe.)
+
+0E16xx00	>= Controls the digital input to the "H" and "L" chips.
+		   These chips control the ZIF socket GND supply.
+		   xx is the ZIF-socket pin that is pulled to GND.
+		   It is calculated as follows:
+		   xx = ZIF_pin_number - 4
+		   Valid ZIF_pin_numbers are:
+		   0,5,14-20,24,26-29,33-35
+		   0 is a special value for not assigning GND to any pin.
+		   If the pin number is 0 (=none), 4 is not subtracted.
+
+0E220000...	>= Program the FPGA. 60bytes of data is appended.
+
+1B		>= Flush (and/or commit) command
diff --git a/reverse-engineering/schematics/top2049.pro b/reverse-engineering/schematics/top2049.pro
new file mode 100644
index 0000000..f226ffb
--- /dev/null
+++ b/reverse-engineering/schematics/top2049.pro
@@ -0,0 +1,6 @@
+update=25/1/2010-10:31:15
+last_client=kicad
+[general]
+version=1
+RootSch=top2049.sch
+BoardNm=top2049.brd
diff --git a/reverse-engineering/schematics/top2049.sch b/reverse-engineering/schematics/top2049.sch
new file mode 100644
index 0000000..89fb3f2
--- /dev/null
+++ b/reverse-engineering/schematics/top2049.sch
@@ -0,0 +1,748 @@
+EESchema Schematic File Version 1
+LIBS:power,device,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,contrib,valves
+EELAYER 43  0
+EELAYER END
+$Descr A3 16535 11700
+Sheet 1 1
+Title "TOP2049 "L" and "H" chip connections"
+Date "25 jan 2010"
+Rev "1"
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+	6250 5050 13200 5050
+Wire Wire Line
+	13200 5050 13200 6950
+Wire Wire Line
+	13400 7500 13400 7250
+Wire Wire Line
+	12700 7500 12700 7250
+Wire Wire Line
+	6250 5650 11800 5650
+Wire Wire Line
+	11800 5650 11800 6950
+Wire Wire Line
+	11600 7250 11600 7500
+Wire Wire Line
+	10400 6950 10400 5850
+Wire Wire Line
+	10400 5850 6250 5850
+Wire Wire Line
+	11300 7500 11300 7250
+Wire Wire Line
+	10200 7500 10200 7250
+Wire Wire Line
+	9500 7250 9500 7500
+Wire Wire Line
+	5550 5750 5400 5750
+Wire Wire Line
+	5400 5750 5400 6150
+Wire Wire Line
+	5400 6150 9000 6150
+Wire Wire Line
+	9000 6150 9000 6950
+Wire Wire Line
+	8800 7500 8800 7250
+Wire Wire Line
+	8100 7500 8100 7250
+Wire Wire Line
+	7800 7500 7800 7250
+Wire Wire Line
+	7600 6950 7600 6350
+Wire Wire Line
+	7600 6350 5200 6350
+Wire Wire Line
+	5200 6350 5200 5550
+Wire Wire Line
+	5200 5550 5550 5550
+Wire Wire Line
+	7100 7500 7100 7250
+Wire Wire Line
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+Wire Wire Line
+	6200 6950 6200 6550
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	5000 5050 5550 5050
+Wire Wire Line
+	6250 5150 6550 5150
+Wire Wire Line
+	6550 5150 6550 4150
+Connection ~ 4600 4150
+Wire Wire Line
+	6550 4150 4600 4150
+Connection ~ 4900 4050
+Wire Wire Line
+	4900 3950 4900 5250
+Wire Wire Line
+	2900 7250 2900 7500
+Wire Wire Line
+	3800 5550 3250 5550
+Wire Wire Line
+	3250 5550 3250 6500
+Wire Wire Line
+	3250 6500 2700 6500
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	3450 6400 3450 5750
+Wire Wire Line
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+Wire Wire Line
+	4100 6400 4100 6950
+Wire Wire Line
+	5700 7500 5700 7250
+Wire Wire Line
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+Wire Wire Line
+	3900 7500 3900 7250
+Wire Wire Line
+	4300 7500 4300 7250
+Wire Wire Line
+	3450 5750 3800 5750
+Wire Wire Line
+	3200 5450 3800 5450
+Connection ~ 5400 5250
+Connection ~ 5400 4600
+Wire Wire Line
+	5400 4600 5400 5350
+Connection ~ 3650 5250
+Wire Wire Line
+	3650 5350 3650 4600
+Connection ~ 3650 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5400 5350
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+NoConn ~ 6250 5350
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+L TST P?
+U 1 1 4B5DB472
+P 13400 7500
+F 0 "P?" H 13400 7800 40  0000 C C
+F 1 "ZIF PIN26" H 13400 7750 30  0000 C C
+	1    13400 7500
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+F 1 "ZIF PIN16" H 12700 7750 30  0000 C C
+	1    12700 7500
+	-1   0    0    1   
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+L GND #PWR?
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+F 1 "GND" H 13000 7430 30  0001 C C
+	1    13000 7500
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+	1    12300 7500
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+F 0 "Q22G" H 13350 7150 50  0000 C C
+F 1 "NPN" H 13102 7300 50  0000 C C
+	1    13200 7150
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+$EndComp
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+U 1 1 4B5DB41E
+P 12500 7150
+F 0 "Q12G" H 12650 7150 50  0000 C C
+F 1 "NPN" H 12402 7300 50  0000 C C
+	1    12500 7150
+	0    1    1    0   
+$EndComp
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+F 0 "#PWR?" H 11600 7500 30  0001 C C
+F 1 "GND" H 11600 7430 30  0001 C C
+	1    11600 7500
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+$EndComp
+$Comp
+L GND #PWR?
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+	1    10900 7500
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+$Comp
+L TST P?
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+F 1 "ZIF PIN15" H 12000 7750 30  0000 C C
+	1    12000 7500
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+$EndComp
+$Comp
+L TST P?
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+$Comp
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+P 10600 7500
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+F 1 "ZIF PIN18" H 10600 7750 30  0000 C C
+	1    10600 7500
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+$EndComp
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+U 1 1 4B5DB20F
+P 9900 7500
+F 0 "P?" H 9900 7800 40  0000 C C
+F 1 "ZIF PIN35" H 9900 7750 30  0000 C C
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+F 1 "NPN" H 11702 7300 50  0000 C C
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+U 1 1 4B5DAEED
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+F 1 "NPN" H 8902 7300 50  0000 C C
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+F 1 "NPN" H 8202 7300 50  0000 C C
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+F 1 "ZIF PIN14" H 7800 7750 30  0000 C C
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+P 7400 7500
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+$EndComp
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+L TST P?
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+P 7100 7500
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+F 1 "ZIF PIN34" H 7100 7750 30  0000 C C
+	1    7100 7500
+	-1   0    0    1   
+$EndComp
+$Comp
+L TST P?
+U 1 1 4B5DAC5C
+P 6400 7500
+F 0 "P?" H 6400 7800 40  0000 C C
+F 1 "ZIF PIN27" H 6400 7750 30  0000 C C
+	1    6400 7500
+	-1   0    0    1   
+$EndComp
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+U 1 1 4B5DAC56
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+F 0 "#PWR?" H 6000 7500 30  0001 C C
+F 1 "GND" H 6000 7430 30  0001 C C
+	1    6000 7500
+	1    0    0    -1  
+$EndComp
+NoConn ~ 4500 5050
+$Comp
+L TST P?
+U 1 1 4B5DAAA1
+P 4600 3500
+F 0 "P?" H 4600 3800 40  0000 C C
+F 1 "MICROCTRLR P1.7" H 4600 3750 30  0000 C C
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+F 1 "MICROCTRLR ALE" H 4900 4200 30  0000 C C
+	1    4900 3950
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+$EndComp
+NoConn ~ 4500 5350
+NoConn ~ 4500 5550
+NoConn ~ 4500 5650
+NoConn ~ 4500 5750
+$Comp
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+U 1 1 4B5DA855
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+F 0 "P?" H 2900 7800 40  0000 C C
+F 1 "ZIF PIN28" H 2900 7750 30  0000 C C
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+F 1 "ZIF PIN33" H 3600 7750 30  0000 C C
+	1    3600 7500
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+	1    5300 7500
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+$EndComp
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+F 0 "#PWR?" H 4600 7500 30  0001 C C
+F 1 "GND" H 4600 7430 30  0001 C C
+	1    4600 7500
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+F 1 "GND" H 3900 7430 30  0001 C C
+	1    3900 7500
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+L TST P?
+U 1 1 4B5D7AA8
+P 5000 7500
+F 0 "P?" H 5000 7800 40  0000 C C
+F 1 "ZIF PIN19" H 5000 7750 30  0000 C C
+	1    5000 7500
+	-1   0    0    1   
+$EndComp
+$Comp
+L TST P?
+U 1 1 4B5D7A0D
+P 4300 7500
+F 0 "P?" H 4300 7800 40  0000 C C
+F 1 "ZIF PIN17" H 4300 7750 30  0000 C C
+	1    4300 7500
+	-1   0    0    1   
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+L NPN Q30G
+U 1 1 4B5D798E
+P 6900 7150
+F 0 "Q30G" H 7050 7150 50  0000 C C
+F 1 "NPN" H 6802 7300 50  0000 C C
+	1    6900 7150
+	0    1    1    0   
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+L NPN Q23G
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+F 1 "NPN" H 6102 7300 50  0000 C C
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+	0    1    1    0   
+$EndComp
+$Comp
+L NPN Q1G
+U 1 1 4B5D797B
+P 5500 7150
+F 0 "Q1G" H 5650 7150 50  0000 C C
+F 1 "NPN" H 5402 7300 50  0000 C C
+	1    5500 7150
+	0    1    1    0   
+$EndComp
+$Comp
+L NPN Q13
+U 1 1 4B5D7976
+P 4800 7150
+F 0 "Q13" H 4950 7150 50  0000 C C
+F 1 "NPN" H 4702 7300 50  0000 C C
+	1    4800 7150
+	0    1    1    0   
+$EndComp
+$Comp
+L NPN Q13G
+U 1 1 4B5D796F
+P 4100 7150
+F 0 "Q13G" H 4250 7150 50  0000 C C
+F 1 "NPN" H 4002 7300 50  0000 C C
+	1    4100 7150
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 4B5D7899
+P 5450 5450
+F 0 "#PWR?" H 5450 5450 30  0001 C C
+F 1 "GND" H 5450 5380 30  0001 C C
+	1    5450 5450
+	0    1    1    0   
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 4B5D7889
+P 3200 5450
+F 0 "#PWR?" H 3200 5450 30  0001 C C
+F 1 "GND" H 3200 5380 30  0001 C C
+	1    3200 5450
+	0    1    1    0   
+$EndComp
+$Comp
+L +3.3V #PWR?
+U 1 1 4B5D778C
+P 3050 5350
+F 0 "#PWR?" H 3050 5310 30  0001 C C
+F 1 "+3.3V" H 3050 5460 30  0000 C C
+	1    3050 5350
+	0    -1   -1   0   
+$EndComp
+NoConn ~ 3800 5150
+NoConn ~ 3800 5050
+$Comp
+L DIL18 U2
+U 1 1 4B5D763E
+P 5900 5450
+F 0 "U2" H 5900 6000 70  0000 C C
+F 1 "H-chip" H 5900 4900 70  0000 C C
+	1    5900 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L DIL18 U2B
+U 1 1 4B5D763B
+P 4150 5450
+F 0 "U2B" H 4150 6000 70  0000 C C
+F 1 "L-chip" H 4150 4900 70  0000 C C
+	1    4150 5450
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/reverse-engineering/vccx_layouts_dump b/reverse-engineering/vccx_layouts_dump
new file mode 100755
index 0000000..778004e
--- /dev/null
+++ b/reverse-engineering/vccx_layouts_dump
@@ -0,0 +1,135 @@
+#!/usr/bin/env python
+
+# This is a dump of the VCCX layouts. The array index is the
+# layout ID and the array entries are the inverted shift
+# register outputs. The least significant byte is the first
+# shift register in the chain.
+
+vccx_layouts = [
+	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+	0x000000, 0x000000, 0x000001, 0x000000, 0x000000, 0x002000,
+	0x000000, 0x000002, 0x000000, 0x000000, 0x080000, 0x000004,
+	0x000000, 0x000000, 0x010000, 0x004000, 0x000000, 0x000000,
+	0x000008, 0x000010, 0x000020, 0x000040, 0x000080, 0x000000,
+	0x000100, 0x000000, 0x000200, 0x000000, 0x000400, 0x000000,
+	0x000800, 0x000000, 0x008000, 0x000000, 0x001000, 0x000000,
+	0x020000, 0x000000, 0x040000, #0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x012000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000, 0x000000, 0x000000,
+#	0x000000, 0x000000, 0x000000, 0x000000,
+]
+
+shreg2zif_map = {
+	# SHREG.PIN  :  ZIF_PIN
+
+	# left side
+	# 1
+	# 2
+	# 3
+	# 4
+	# 5
+	# 6
+	# 7
+	# 8
+	# 9
+	# 10
+	# 11
+	"0.0" : 12,	# Q8C
+	# 13
+	# 14
+	"1.5" : 15,	# Q11C
+	# 16
+	"0.1" : 17,	# Q13C
+	# 18
+	# 19
+	"2.3" : 20,	# Q16C
+	"0.2" : 21,	# Q17C
+	# 22
+	# 23
+	"2.0" : 24,	# Q20C
+
+	# right side
+	"2.2" : 48,	# Q44C
+	# 47		
+	"2.1" : 46,	# Q42C
+	# 45		
+	"1.4" : 44,	# Q40C
+	# 43		
+	"1.7" : 42,	# Q38C
+	# 41		
+	"1.3" : 40,	# Q36C
+	# 39		
+	"1.2" : 38,	# Q34C
+	# 37		
+	"1.1" : 36,	# Q32C
+	# 35		
+	"1.0" : 34,	# Q30C
+	# 33		
+	"0.7" : 32,	# Q28C
+	"0.6" : 31,	# Q27C
+	"0.5" : 30,	# Q26C
+	"0.4" : 29,	# Q25C
+	"0.3" : 28,	# Q24C
+	# 27		
+	# 26		
+	"1.6" : 25,	# Q21C
+}
+
+def printLayouts():
+	for layoutNr in range(0, len(vccx_layouts)):
+		layout = vccx_layouts[layoutNr]
+		print "ZIF socket VCCX layout %d:" % layoutNr
+		hotPins = []
+		for reg in range(0, 3):
+			for bit in range(0, 8):
+				mask = (1 << bit) << (reg * 8)
+				if layout & mask == 0:
+					continue
+				string = "%d.%d" % (reg, bit)
+				zifPin = shreg2zif_map[string]
+				hotPins.append(zifPin)
+		print "         o---------o"
+		for pin in range(1, 25):
+			left = "      "
+			right = ""
+			if pin in hotPins:
+				left = "VCCX >"
+			if (49 - pin) in hotPins:
+				right = "< VCCX"
+			print "%s   | %2d | %2d |   %s" % (left, pin, 49 - pin, right)
+		print "         o---------o"
+		print ""
+
+printLayouts()
diff --git a/reverse-engineering/vpp_layouts_dump b/reverse-engineering/vpp_layouts_dump
new file mode 100755
index 0000000..c209318
--- /dev/null
+++ b/reverse-engineering/vpp_layouts_dump
@@ -0,0 +1,144 @@
+#!/usr/bin/env python
+
+# This is a dump of the VPP layouts. The array index is the
+# layout ID and the array entries are the inverted shift
+# register outputs. The least significant byte is the first
+# shift register in the chain.
+
+vpp_layouts = [
+	0x00000000, 0x02000000, 0x03000000, 0x03000008, 0x03000008,
+	0x03100008, 0x03100008, 0x03120008, 0x03130008, 0x03134008,
+	0x03136008, 0x03137008, 0x03137208, 0x03137208, 0x03137308,
+	0x03137328, 0x03137328, 0x03137328, 0x03137328, 0x03137328,
+	0x03137329, 0x03137329, 0x0313732B, 0x0313732B, 0x0313732B,
+	0x0313732B, 0x0313732F, 0x0313733F, 0x0313737F, 0x031373FF,
+	0x031377FF, 0x03137FFF, 0x03137FFF, 0x0313FFFF, 0x0317FFFF,
+	0x031FFFFF, 0x031FFFFF, 0x033FFFFF, 0x033FFFFF, 0x037FFFFF,
+	0x03FFFFFF, 0x03FFFFFF, 0x07FFFFFF, 0x0FFFFFFF, 0x8FFFFFFF,
+	0xCFFFFFFF, 0xEFFFFFFF, 0xFFFFFFFF, #0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+#	0xFFFFFFFF,
+]
+
+shreg2zif_map = {
+	# SHREG.PIN  :  ZIF_PIN
+
+	# left side
+	"3.6" : 1,	# QP31
+	"3.5" : 2,	# QP30
+	"3.4" : 3,	# QP29
+	# 4
+	"3.1" : 5,	# QP26
+	"3.0" : 6,	# QP25
+	"0.3" : 7,	# QP4
+	# 8
+	"2.4" : 9,	# QP21
+	# 10
+	"2.1" : 11,	# QP18
+	"2.0" : 12,	# QP17
+	"1.6" : 13,	# QP15
+	"1.5" : 14,	# QP14
+	"1.4" : 15,	# QP13
+	"1.1" : 16,	# QP10
+	# 17
+	"1.0" : 18,	# QP9
+	"0.5" : 19,	# QP6
+	# 20
+	# 21
+	# 22
+	# 23
+	"0.0" : 24,	# QP1
+
+	# right side
+	"3.7" : 48,	# QP32	
+	"3.3" : 47,	# QP28	
+	"3.2" : 46,	# QP27	
+	# 45		
+	"2.7" : 44,	# QP24	
+	"2.6" : 43,	# QP23	
+	# 42		
+	"2.5" : 41,	# QP22	
+	# 40		
+	"2.3" : 39,	# QP20	
+	"2.2" : 38,	# QP19	
+	"1.7" : 37,	# QP16	
+	# 36		
+	"1.3" : 35,	# QP12	
+	"1.2" : 34,	# QP11	
+	"0.7" : 33,	# QP8	
+	"0.6" : 32,	# QP7	
+	"0.4" : 31,	# QP5	
+	"0.2" : 30,	# QP3	
+	# 29		
+	# 28		
+	# 27		
+	"0.1" : 26,	# QP2	
+	# 25		
+}
+
+def printLayouts():
+	for layoutNr in range(0, len(vpp_layouts)):
+		layout = vpp_layouts[layoutNr]
+		print "ZIF socket VPP layout %d:" % layoutNr
+		hotPins = []
+		for reg in range(0, 4):
+			for bit in range(0, 8):
+				mask = (1 << bit) << (reg * 8)
+				if layout & mask == 0:
+					continue
+				string = "%d.%d" % (reg, bit)
+				zifPin = shreg2zif_map[string]
+				hotPins.append(zifPin)
+		print "        o---------o"
+		for pin in range(1, 25):
+			left = "     "
+			right = ""
+			if pin in hotPins:
+				left = "VPP >"
+			if (49 - pin) in hotPins:
+				right = "< VPP"
+			print "%s   | %2d | %2d |   %s" % (left, pin, 49 - pin, right)
+		print "        o---------o"
+		print ""
+
+printLayouts()
diff --git a/reverse-engineering/zif_connections.ods b/reverse-engineering/zif_connections.ods
new file mode 100644
index 0000000..df5ee38
Binary files /dev/null and b/reverse-engineering/zif_connections.ods differ
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