summaryrefslogtreecommitdiffstats
path: root/reverse-engineering/dump-parser.py
blob: 7fadcd03e3d65f0980582afb5cfa58389320700b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
#!/usr/bin/env python
"""
#    TOP2049 Open Source programming suite
#
#    USB dump parser
#
#    Copyright (c) 2010 Michael Buesch <m@bues.ch>
#
#    This program is free software; you can redistribute it and/or modify
#    it under the terms of the GNU General Public License as published by
#    the Free Software Foundation; either version 2 of the License, or
#    (at your option) any later version.
#
#    This program is distributed in the hope that it will be useful,
#    but WITHOUT ANY WARRANTY; without even the implied warranty of
#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#    GNU General Public License for more details.
#
#    You should have received a copy of the GNU General Public License along
#    with this program; if not, write to the Free Software Foundation, Inc.,
#    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
"""

import sys
import re

packethdr_re = re.compile(r"Dev\s+([0-9a-fA-F]{4,4}):([0-9a-fA-F]{4,4})\s+EP([0-9a-fA-F]+)\s+(\w+)\s(\w+)\s+len=(\d+)")
payload_re = re.compile(r"\[([0-9a-fA-F]+)\]:\s+([0-9a-fA-F\s]+)\s+.+")


def generateHexdump(mem):
	def toAscii(char):
		if char >= 32 and char <= 126:
			return chr(char)
		return "."

	ret = ""
	ascii = ""
	for i in range(0, len(mem)):
		if i % 16 == 0 and i != 0:
			ret += "  " + ascii + "\n"
			ascii = ""
		if i % 16 == 0:
			ret += "0x%04X:  " % i
		c = mem[i]
		ret += "%02X" % c
		if (i % 2 != 0):
			ret += " "
		ascii += toAscii(c)
	ret += "  " + ascii + "\n\n"
	return ret

def dumpMem(mem):
	sys.stdout.write(generateHexdump(mem))

def dumpInstr(instr, description):
	for i in instr:
		sys.stdout.write("%02X" % i)
	sys.stdout.write("  " * (10 - len(instr)))
	sys.stdout.write(": " + description)
	sys.stdout.write("\n")

def parseBulkIn(data):
	if len(data) == 64:
		print "Read buffer register"
		dumpMem(data)

def parseBulkOut(data):
	i = 0
	while i < len(data):
		if data[i] == 0x00:
			dumpInstr(data[i:i+1], "Delay 4 usec")
		elif data[i] == 0x01:
			dumpInstr(data[i:i+1], "Read byte from FPGA")
		elif data[i] == 0x07:
			dumpInstr(data[i:i+1], "Read buffer register request")
		elif data[i] == 0x0A:
			dumpInstr(data[i:i+3], "Write 0x%02X to the FPGA at address 0x%02X" % (data[i+2], data[i+1]))
			i += 2
		elif data[i] == 0x0B:
			dumpInstr(data[i:i+2], "Read data from FPGA at address 0x%02X" % (data[i+1]))
			i += 1
		elif data[i] == 0x0E and data[i+1] == 0x11:
			dumpInstr(data[i:i+4], "Read device ID request")
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x12:
			centivolts = data[i+2]
			dumpInstr(data[i:i+4], "Set VPP to %.2f Volts" % (float(centivolts) / 10))
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x13:
			centivolts = data[i+2]
			dumpInstr(data[i:i+4], "Set VCCX to %.2f Volts" % (float(centivolts) / 10))
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x14:
			dumpInstr(data[i:i+4], "Loading VPP layout %d" % data[i+1])
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x15:
			dumpInstr(data[i:i+4], "Loading VCCX layout %d" % data[i+1])
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x16:
			dumpInstr(data[i:i+4], "Loading GND layout %d" % data[i+1])
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x20:
			dumpInstr(data[i:i+4], "Unknown 0x0E20%02X%02X" % (data[i+2], data[i+3]))
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x21:
			dumpInstr(data[i:i+4], "Initiate FPGA programming")
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x22:
			dumpInstr(data[i:i+4], "Upload FPGA configuration data")
			i += 63
		elif data[i] == 0x0E and data[i+1] == 0x25:
			dumpInstr(data[i:i+4], "Unknown 0x0E25")
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x28:
			op = "Disable"
			if data[i+2] == chr(0):
				op = "Enable"
			dumpInstr(data[i:i+4], "%s the ZIF socket" % op)
			i += 3
		elif data[i] == 0x0E and data[i+1] == 0x1F:
			dumpInstr(data[i:i+4], "Unknown 0x0E1F")
			i += 3
		elif data[i] == 0x0D:
			dumpInstr(data[i:i+1], "Unknown 0x0D")
		elif data[i] == 0x10:
			dumpInstr(data[i:i+2], "Write 0x%02X to the FPGA at address 0x10" % data[i+1])
			i += 1
		elif data[i] == 0x19:
			dumpInstr(data[i:i+1], "Unknown 0x19")
		elif data[i] == 0x1B:
			dumpInstr(data[i:i+1], "Delay 10 msec")
		elif data[i] == 0x34:
			dumpInstr(data[i:i+1], "Unknown 0x34")
		elif data[i] == 0x38:
			dumpInstr(data[i:i+2], "Unknown 0x38")
			i += 1
		elif data[i] == 0x39:
			dumpInstr(data[i:i+1], "Unknown 0x39")
		elif data[i] == 0x4A:
			dumpInstr(data[i:i+2], "Unknown 0x4A")
			i += 1
		elif data[i] == 0x4B:
			dumpInstr(data[i:i+2], "Unknown 0x4B")
			i += 1
		else:
			print "UNKNOWN INSTRUCTION 0x%02X. Aborting..." % data[i]
			for j in range(i, len(data)):
				sys.stdout.write("%02X " % data[j])
			print ""
			sys.exit(1)
		i += 1

def parseDumpFile(fd):
	transtype = None
	bulkData = []
	for line in fd.readlines():
		if transtype == "BULK":
			# Bulk IN or OUT transfer
			m = payload_re.match(line)
			if m:
				offset = int(m.group(1), 16)
				dataString = m.group(2)

				dataString = dataString.replace(" ", "").strip()
				assert(len(dataString) % 2 == 0)
				for i in range(0, len(dataString), 2):
					byteStr = dataString[i:i+2]
					bulkData.append(int(byteStr, 16))
			else:
				# Transfer done
				assert(len(bulkData) == length)
				if direction == "IN":
					parseBulkIn(bulkData)
				elif direction == "OUT":
					parseBulkOut(bulkData)
				else:
					assert(0)
				transtype = None
				bulkData = []

		m = packethdr_re.match(line)
		if m:
			vendor = int(m.group(1), 16)
			device = int(m.group(2), 16)
			ep = int(m.group(3), 16)
			transtype = m.group(4).upper()
			direction = m.group(5).upper()
			length = int(m.group(6))

def usage():
	print "dump-parser.py file.dump"

def main(argv):
	if len(argv) != 2:
		usage()
		return 1

	fd = file(argv[1])
	parseDumpFile(fd)

	return 0

if __name__ == "__main__":
	sys.exit(main(sys.argv))
bues.ch cgit interface