#include FakeIO MCUCSR; FakeIO PORTB; FakeIO PORTC; FakeIO PORTD; FakeIO DDRB; FakeIO DDRC; FakeIO DDRD; FakeIO PINB; FakeIO PINC; FakeIO PIND; FakeIO TIMSK0; FakeIO TIFR0; FakeIO TIMSK1; FakeIO TIFR1; FakeIO SREG; FakeIO OCR0A; FakeIO OCR0B; FakeIO TCNT0; FakeIO TCCR0A; FakeIO TCCR0B; FakeIO OCR1A; FakeIO OCR1B; FakeIO ICR1; FakeIO TCNT1; FakeIO TCCR1A; FakeIO TCCR1B; FakeIO TCCR1C; FakeIO ADC; FakeIO ADCSRA; FakeIO ADCSRB; FakeIO ADMUX; FakeIO DIDR0; FakeIO DIDR1; FakeIO EECR; FakeIO EEDR; FakeIO EEAR; FakeIO UCSR0A; FakeIO UCSR0B; FakeIO UCSR0C; FakeIO UBRR0; FakeIO UDR0; void fakeio_reset_all(void) { MCUCSR.reset(); PORTB.reset(); PORTC.reset(); PORTD.reset(); DDRB.reset(); DDRC.reset(); DDRD.reset(); PINB.reset(); PINC.reset(); PIND.reset(); TIMSK0.reset(); TIFR0.reset(); TIMSK1.reset(); TIFR1.reset(); SREG.reset(); OCR0A.reset(); OCR0B.reset(); TCNT0.reset(); TCCR0A.reset(); TCCR0B.reset(); OCR1A.reset(); OCR1B.reset(); ICR1.reset(); TCNT1.reset(); TCCR1A.reset(); TCCR1B.reset(); TCCR1C.reset(); ADC.reset(); ADCSRA.reset(); ADCSRB.reset(); ADMUX.reset(); DIDR0.reset(); DIDR1.reset(); EECR.reset(); EEDR.reset(); EEAR.reset(); UCSR0A.reset(); UCSR0B.reset(); UCSR0C.reset(); UBRR0.reset(); UDR0.reset(); }