Generator for CRC HDL code

This code generator creates HDL code (Verilog, VHDL or MyHDL) for any CRC algorithm.
The HDL code is synthesizable and combinatorial. That means the calculation runs in one clock cycle on an FPGA.

Please select the CRC parameters and the output language settings below.
Then press "generate" to generate the code.

Select CRC algorithm:
Bits:
Polynomial:

Properties:
Input data word width (bits):
Function/module name:
Data parameter name:
CRC input parameter name:
CRC output parameter name:

Select output language:

The online generator is restricted to a maximum of 128 bit CRC length and a maximum of 64 bit input word length. The downloadable offline version (see below) does not have these restrictions.

The development source code of crcgen can be downloaded using the Git version control system as follows:

git clone https://git.bues.ch/git/crcgen.git

To browse the Git repository online, go to the repository web interface.
Or download the compressed snapshot.
A mirror of the repository is available on GitHub, GitLab, Bitbucket and on NotABug.org.
If you want to contribute to crcgen, please read the contribution guidelines first.

crcgen is stable/production quality software.
That means its features are well tested and the remaining amount of bugs probably is minor. The documentation is not complete.

If you find any bugs in crcgen or if you have any suggestion for new features, we would like to hear from you.
Your help is greatly appreciated and will help to create better software and improve the overall experience for everybody. So don't hesitate to report anything that that limits your crcgen usage.

If you have got any code improvements or other improvements that should be merged into the project, please send such enhancements to the crcgen maintainer.

Please read the contribution guidelines first.

The generated code is Public Domain.
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
USE OR PERFORMANCE OF THIS SOFTWARE.

Copyright (C) Michael Büsch
Licensed under the terms of the GNU General Public License version 2 or (at your option) any later version. See the sourcecode for details.

Updated: Saturday 17 July 2021 13:38 (UTC)
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