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crcgen.git
flexiblesizes
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vhdl
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
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flexiblesizes
generator test: Add support for data sizes != 8
Michael Buesch
3 years
master
Bump version
Michael Buesch
11 months
vhdl
generator: Add VHDL support
Michael Buesch
3 years
Tag
Download
Author
Age
crcgen-2.6
crcgen-2.6.tar.xz
crcgen-2.6.zip
Michael Buesch
11 months
crcgen-2.5
crcgen-2.5.tar.xz
crcgen-2.5.zip
Michael Buesch
17 months
crcgen-2.4
crcgen-2.4.tar.xz
crcgen-2.4.zip
Michael Buesch
22 months
crcgen-2.3
crcgen-2.3.tar.xz
crcgen-2.3.zip
Michael Buesch
22 months
crcgen-2.2
crcgen-2.2.tar.xz
crcgen-2.2.zip
Michael Buesch
3 years
crcgen-2.1
crcgen-2.1.tar.xz
crcgen-2.1.zip
Michael Buesch
3 years
crcgen-2.0
crcgen-2.0.tar.xz
crcgen-2.0.zip
Michael Buesch
3 years
crcgen-1.1
crcgen-1.1.tar.xz
crcgen-1.1.zip
Michael Buesch
4 years
crcgen-1.0
crcgen-1.0.tar.xz
crcgen-1.0.zip
Michael Buesch
5 years
Age
Commit message
Author
Files
Lines
2023-10-13
Bump version
HEAD
crcgen-2.6
master
Michael Buesch
1
-1
/
+1
2023-07-16
Fix incorrect MyHDL 'next' use
Michael Buesch
1
-1
/
+1
2023-04-15
release script: Cleanup
crcgen-2.5
Michael Buesch
1
-2
/
+1
2023-04-15
Remove unnecessary parenthesis
Michael Buesch
1
-1
/
+1
2023-04-15
Bump version
Michael Buesch
1
-1
/
+1
2023-04-15
Support polynomial conversion in both directions
Michael Buesch
1
-8
/
+35
2023-04-15
Use private fields in bit classes
Michael Buesch
1
-12
/
+20
2023-04-15
setup: Add python version
Michael Buesch
1
-0
/
+1
2023-04-15
Remove old py2 compat oldstyle class
Michael Buesch
2
-5
/
+5
2023-04-15
Add command line help description
Michael Buesch
1
-1
/
+3
[...]
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