1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
|
/*
* TOP2049 Open Source programming suite
*
* Atmel AT89S5X DIP40
* FPGA bottomhalf implementation
*
* Copyright (c) 2010 Guido
* Copyright (c) 2010 Michael Buesch <m@bues.ch>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
/* The runtime ID and revision. */
`define RUNTIME_ID 16'h0005
`define RUNTIME_REV 16'h01
module at89s5xdip40(data, ale, write, read, osc_in, zif);
inout [7:0] data;
input ale;
input write;
input read;
input osc_in; /* 24MHz oscillator */
inout [48:1] zif;
/* Interface to the microcontroller */
wire read_oe; /* Read output-enable */
reg [7:0] address; /* Cached address value */
reg [7:0] read_data; /* Cached read data */
wire low, high; /* Constant lo/hi */
/* Programmer context */
reg [1:0] prog_busy;
reg [3:0] prog_command;
reg [3:0] prog_state;
reg [3:0] prog_count;
reg prog_err;
/* DUT signals */
reg [7:0] dut_data;
reg [13:0] dut_addr;
reg dut_p26;
reg dut_p27;
reg dut_p33;
reg dut_p36;
reg dut_p37;
reg dut_psen;
reg dut_prog;
reg dut_vpp;
reg dut_rst;
wire dut_clock;
assign low = 0;
assign high = 1;
initial begin
prog_busy <= 0;
prog_command <= 0;
prog_state <= 0;
prog_err <= 0;
prog_count <= 0;
dut_data <= 0;
dut_addr <= 0;
dut_p26 <= 0;
dut_p27 <= 0;
dut_p33 <= 0;
dut_p36 <= 0;
dut_p37 <= 0;
dut_psen <= 0;
dut_prog <= 0;
dut_vpp <= 0;
dut_rst <= 0;
end
/* The delay counter. Based on the 24MHz input clock. */
reg [15:0] delay_count;
wire osc;
assign dut_clock=osc;
IBUF osc_ibuf(.I(osc_in), .O(osc));
always @(posedge osc) begin
if (delay_count == 0) begin
if (prog_busy[0] != prog_busy[1]) begin
/* busy0 != busy1 indicates that a command is running.
* Continue executing it... */
case (prog_command)
1: begin /* Set P3.2 after init */
dut_prog <= 1;
prog_busy[1] <= prog_busy[0];
end
2: begin /* clear P3.2 before shutdown */
dut_prog <= 0;
prog_busy[1] <= prog_busy[0];
end
3: begin /* do nPROG pulsep with wait for ready */
case (prog_state)
0: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*2us (48 tcl) wait*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24;/* each 1us */
dut_prog <= 0;
prog_state <= 2;
end
2: begin /* raise dut_prog */
dut_prog <= 1;
prog_state <= 3;
prog_count <= 12;
delay_count <= 48;/*2us (48 tcl) wait*/
end
3: begin /* wait for ready (zif[14]) == 1 */
if (zif[14] == 0) begin
delay_count <= 80; /* each 3330ns */
prog_count <= prog_count - 1;
if (prog_count == 0) begin
prog_err <= 1;
prog_state <= 4;
end
end
else begin
prog_state <= 4;
end
end
4: begin /* finish */
prog_state <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
4: begin /* do nPROG pulsep */
case (prog_state)
0: begin
dut_prog <= 1;
prog_state <= 1;
delay_count <= 48;/*48tcy, 2us*/
prog_err <= 0;
end
1: begin /* pulse */
delay_count <= 24; /* 1us each */
dut_prog <= 0;
prog_state <= 2;
end
2: begin
dut_prog <= 1;
prog_state <= 3;
delay_count <= 48;/*48tcy, 2us*/
end
3: begin
prog_busy[1] <= prog_busy[0];
prog_state <= 0;
end
endcase
end
5: begin /* set dut_vpp */
dut_vpp <= 1;
prog_busy[1] <= prog_busy[0];
end
6: begin /* clear dut_vpp */
dut_vpp <= 0;
prog_busy[1] <= prog_busy[0];
end
endcase
end
end else begin
delay_count <= delay_count - 1;
end
end
always @(posedge write) begin
case (address)
8'h10: begin
/* Data write */
dut_data <= data;
end
8'h11: begin
/* Address LSB write */
dut_addr[7:0] <= data;
end
8'h12: begin
/* Address MSB write */
dut_addr[13:8] <= data[5:0];
end
8'h13: begin
/* Run a command. */
prog_command <= data;
prog_busy[0] <= ~prog_busy[1];
end
8'h16: begin
/* Set P26, P27, P33, P36, P37, dut_psen, dut_rst */
dut_p26 <= data[0];
dut_p27 <= data[1];
dut_p33 <= data[2];
dut_p36 <= data[3];
dut_p37 <= data[4];
dut_psen <= data[5];
dut_rst <= data[6];
end
endcase
end
always @(negedge read) begin
case (address)
8'h10: begin
/* Data read */
read_data[7] <= zif[36];
read_data[6] <= zif[37];
read_data[5] <= zif[38];
read_data[4] <= zif[39];
read_data[3] <= zif[40];
read_data[2] <= zif[41];
read_data[1] <= zif[42];
read_data[0] <= zif[43];
end
8'h12: begin
/* Read status */
read_data[0] <= (prog_busy[0] != prog_busy[1]);
read_data[1] <= prog_err;
end
8'hFD: read_data <= `RUNTIME_ID & 16'hFF;
8'hFE: read_data <= (`RUNTIME_ID >> 8) & 16'hFF;
8'hFF: read_data <= `RUNTIME_REV;
endcase
end
always @(negedge ale) begin
address <= data;
end
assign read_oe = !read && address[4];
bufif0(zif[1], low, low);
bufif0(zif[2], low, low);
bufif0(zif[3], low, low);
bufif0(zif[4], low, low);
bufif0(zif[5], dut_addr[0], dut_p26);
bufif0(zif[6], dut_addr[1], dut_p26);
bufif0(zif[7], dut_addr[2], dut_p26);
bufif0(zif[8], dut_addr[3], dut_p26);
bufif0(zif[9], dut_addr[4], dut_p26);
bufif0(zif[10], dut_addr[5], dut_p26);
bufif0(zif[11], dut_addr[6], dut_p26);
bufif0(zif[12], dut_addr[7], dut_p26);
bufif0(zif[13], dut_rst, low); /*Reset*/
bufif0(zif[14], low, high); /* P3.0 */
bufif0(zif[15], low, low); /* P3.1 */
bufif0(zif[16], low, low); /* P3.2 */
bufif0(zif[17], dut_p33, low); /* P3.3 */
bufif0(zif[18], low, low); /* P3.4 */
bufif0(zif[19], low, low); /* P3.5 */
bufif0(zif[20], dut_p36, low); /* P3.6 */
bufif0(zif[21], dut_p37, low); /* P3.7 */
bufif0(zif[22], low, high); /* XTAL2 */
bufif0(zif[23], dut_clock, low); /* XTAL1 */
bufif0(zif[24], low, low); /* GND */
bufif0(zif[25], dut_addr[8], dut_p26); /* P2.0 */
bufif0(zif[26], dut_addr[9], dut_p26); /* P2.1 */
bufif0(zif[27], dut_addr[10], dut_p26); /* P2.2 */
bufif0(zif[28], dut_addr[11], dut_p26); /* P2.3 */
bufif0(zif[29], dut_addr[12], dut_p26); /* P2.4 */
bufif0(zif[30], dut_addr[13], dut_p26); /* P2.5 */
bufif0(zif[31], dut_p26, low); /* P2.6 */
bufif0(zif[32], dut_p27, low); /* P2.7 */
bufif0(zif[33], dut_psen, low); /* !PSEN */
bufif0(zif[34], dut_prog, low); /* !PROG */
bufif0(zif[35], low, dut_vpp); /* VPP/Reset */
bufif0(zif[36], dut_data[7], !(!dut_p26 && dut_p27));
bufif0(zif[37], dut_data[6], !(!dut_p26 && dut_p27));
bufif0(zif[38], dut_data[5], !(!dut_p26 && dut_p27));
bufif0(zif[39], dut_data[4], !(!dut_p26 && dut_p27));
bufif0(zif[40], dut_data[3], !(!dut_p26 && dut_p27));
bufif0(zif[41], dut_data[2], !(!dut_p26 && dut_p27));
bufif0(zif[42], dut_data[1], !(!dut_p26 && dut_p27));
bufif0(zif[43], dut_data[0], !(!dut_p26 && dut_p27));
bufif0(zif[44], high, low); /* VCC */
bufif0(zif[45], low, low);
bufif0(zif[46], low, low);
bufif0(zif[47], low, low);
bufif0(zif[48], low, low);
bufif1(data[0], read_data[0], read_oe);
bufif1(data[1], read_data[1], read_oe);
bufif1(data[2], read_data[2], read_oe);
bufif1(data[3], read_data[3], read_oe);
bufif1(data[4], read_data[4], read_oe);
bufif1(data[5], read_data[5], read_oe);
bufif1(data[6], read_data[6], read_oe);
bufif1(data[7], read_data[7], read_oe);
endmodule
|
