1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
|
# -*- coding: utf-8 -*-
#
# AWL simulator - instructions
#
# Copyright 2012-2017 Michael Buesch <m@bues.ch>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
#
from __future__ import division, absolute_import, print_function, unicode_literals
#from awlsim.common.cython_support cimport * #@cy
from awlsim.common.compat import *
from awlsim.common.exceptions import *
from awlsim.core.instructions.main import * #+cimport
from awlsim.core.operatortypes import * #+cimport
from awlsim.core.operators import * #+cimport
class AwlInsn_MOD(AwlInsn): #+cdef
__slots__ = ()
def __init__(self, cpu, rawInsn=None, **kwargs):
AwlInsn.__init__(self, cpu, AwlInsn.TYPE_MOD, rawInsn, **kwargs)
self.assertOpCount(0)
def run(self): #+cdef
#@cy cdef S7StatusWord s
s = self.cpu.statusWord
accu2, accu1 = self.cpu.accu2.getSignedDWord(),\
self.cpu.accu1.getSignedDWord()
if self.cpu.is4accu:
self.cpu.accu2.setDWord(self.cpu.accu3.getDWord())
self.cpu.accu3.setDWord(self.cpu.accu4.getDWord())
try:
rem = abs(accu2) % abs(accu1)
if accu2 < 0:
rem = -rem
except ZeroDivisionError:
s.A1, s.A0, s.OV, s.OS = 1, 1, 1, 1
return
self.cpu.accu1.setDWord(rem)
if rem == 0:
s.A1, s.A0, s.OV = 0, 0, 0
elif rem < 0:
s.A1, s.A0, s.OV = 0, 1, 0
else:
s.A1, s.A0, s.OV = 1, 0, 0
|
