aboutsummaryrefslogtreecommitdiffstats
BranchCommit messageAuthorAge
flexiblesizesgenerator test: Add support for data sizes != 8Michael Buesch15 months
masterBump versionMichael Buesch11 months
vhdlgenerator: Add VHDL supportMichael Buesch15 months
 
TagDownloadAuthorAge
crcgen-2.2crcgen-2.2.tar.xz  crcgen-2.2.zip  Michael Buesch11 months
crcgen-2.1crcgen-2.1.tar.xz  crcgen-2.1.zip  Michael Buesch15 months
crcgen-2.0crcgen-2.0.tar.xz  crcgen-2.0.zip  Michael Buesch15 months
crcgen-1.1crcgen-1.1.tar.xz  crcgen-1.1.zip  Michael Buesch2 years
crcgen-1.0crcgen-1.0.tar.xz  crcgen-1.0.zip  Michael Buesch3 years
 
AgeCommit messageAuthorFilesLines
2021-11-05Bump versionHEADcrcgen-2.2masterMichael Buesch1-1/+1
2021-11-05Unify indentation among all supported languagesMichael Buesch1-34/+34
2021-11-05Don't generate trailing comma in Verilog module parameter listMichael Buesch1-1/+1
2021-07-17Bump versioncrcgen-2.1Michael Buesch1-1/+1
2021-07-17Add examples to ReadmeMichael Buesch2-2/+34
2021-07-17Fix release scriptMichael Buesch1-1/+1
2021-07-17setup: Update keywordsMichael Buesch1-1/+2
2021-07-17Rename main module to libcrcgenMichael Buesch12-17/+17
2021-07-16Fix VHDL bitsMichael Buesch1-3/+3
2021-07-16Print language in headerMichael Buesch1-8/+8
[...]
 
Clone
https://git.bues.ch/git/crcgen.git
bues.ch cgit interface