summaryrefslogtreecommitdiffstats
path: root/phy_fpga/Makefile
blob: bbee2f7a137e5efeb047a267034a67b7df7e19bd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
NAME		:= pyprofibusphy
TARGET		:= tinyfpga_bx
TARGET_NAME	:= $(TARGET)_$(NAME)

DEBUG		:= 0

YOSYS		:= yosys
NEXTPNR		:= nextpnr
ICEPACK		:= icepack
ICETIME		:= icetime
ICEPLL		:= icepll
TINYPROG	:= tinyprog
PYTHON		:= python3
CAT		:= cat
GREP		:= grep
PRINTF		:= printf
RM		:= rm
FALSE		:= false
TR		:= tr
TEST		:= test
TOUCH		:= touch
GIT		:= git

TARGET_LOWER	:= $(shell $(PRINTF) '%s' '$(TARGET)' | $(TR) A-Z a-z)
TARGET_UPPER	:= $(shell $(PRINTF) '%s' '$(TARGET)' | $(TR) a-z A-Z)

TOP_FILE	:= main.v
TOP_MODULE	:= top_module
PCF_FILE	:= $(TARGET_LOWER).pcf
PLL_MOD_V_FILE	:= pll_mod.v
GENERATED_V	:= crc8_func.v

ifeq ($(TARGET_LOWER),tinyfpga_bx)
YOSYS_SYNTH_CMD	= 'synth_ice40 -top $(TOP_MODULE) -json $(patsubst %.blif,%.json,$@) -blif $@'
PNR_PACKAGE	:= cm81
NEXTPNR_ARCH	:= ice40
DEVICE		:= lp8k
else
$(error TARGET $(TARGET) is invalid)
endif

YOSYS_LOG	:= $(TARGET_NAME)_yosys.log
NEXTPNR_LOG	:= $(TARGET_NAME)_nextpnr.log
ICEPACK_LOG	:= $(TARGET_NAME)_icepack.log
ICETIME_LOG	:= $(TARGET_NAME)_icetime.log
LOG		= >$(1) 2>&1 || ( $(CAT) $(1); $(FALSE) )

.DEFAULT_GOAL := all
all: $(TARGET_NAME).bin $(TARGET_NAME).rpt

ifeq ($(TARGET_LOWER),tinyfpga_bx)
CLK_HZ		:= 16000000
PLL_HZ		:= 24000000
PLL_MOD_V		:= $(PLL_MOD_V_FILE)
CLK_MHZ		:= $(shell expr $(CLK_HZ) / 1000000)
PLL_MHZ		:= $(shell expr $(PLL_HZ) / 1000000)
$(PLL_MOD_V):
	$(ICEPLL) -q -f $@ -m -n pll_module -i $(CLK_MHZ) -o $(PLL_MHZ)
else
CLK_HZ		:= 16000000
PLL_HZ		:= 16000000
PLL_MOD_V		:=
endif

crcgen.stamp:
	$(TEST) -f ./crcgen/crcgen/__main__.py || $(GIT) submodule update --init
	$(TOUCH) $@

crc8_func.v: crcgen.stamp
	PYTHONPATH=./crcgen $(PYTHON) ./crcgen/crcgen --algorithm CRC-8-CCITT --verilog-function --name crc8 > $@

%.blif: $(TOP_FILE) $(wildcard *.v) $(GENERATED_V) $(PLL_MOD_V)
	$(YOSYS) -p 'read_verilog -DTARGET_$(TARGET_UPPER)=1 -DCLK_HZ=$(CLK_HZ) -DPLL_HZ=$(PLL_HZ) $(if $(filter-out 0,$(DEBUG)),-DDEBUG=1) $<' \
		-p $(YOSYS_SYNTH_CMD) \
		$(call LOG,$(YOSYS_LOG))

%.asc: $(PCF_FILE) %.blif
	$(NEXTPNR)-$(NEXTPNR_ARCH) --$(DEVICE) --package $(PNR_PACKAGE) --json $(TARGET_NAME).json --pcf $< --asc $@ \
		$(call LOG,$(NEXTPNR_LOG))

%.bin: %.asc
	$(ICEPACK) $< $@ $(call LOG,$(ICEPACK_LOG))

%.rpt: %.asc %.bin
	$(ICETIME) -d $(DEVICE) -p $(PCF_FILE) -m -t -r $@ $< \
		$(call LOG,$(ICETIME_LOG))
	-@$(PRINTF) '\n'
	-@$(GREP) -i -e 'Total' $@
	-@$(GREP) -i -Ee 'Max frequency|Max delay' $(NEXTPNR_LOG)
	-@$(PRINTF) '\n'
	-@$(GREP) --color=auto -H -n -i -e 'Warning' $(YOSYS_LOG) $(NEXTPNR_LOG) $(ICEPACK_LOG)
	-@$(PRINTF) '\n'
	-@$(GREP) -A6 -i -e 'Device utilisation' $(NEXTPNR_LOG)

install: $(TARGET_NAME).bin
	$(TINYPROG) -p $<

boot:
	$(TINYPROG) -b

clean:
	$(RM) -f *.blif *.json *.asc *.bin *.rpt crcgen.stamp $(YOSYS_LOG) $(NEXTPNR_LOG) $(ICEPACK_LOG) $(ICETIME_LOG) $(GENERATED_V) $(PLL_MOD_V_FILE)

.PHONY: all install boot clean
.PRECIOUS: %.json %.blif %.asc
bues.ch cgit interface