aboutsummaryrefslogtreecommitdiffstats
path: root/schematics-attiny/simplepwm-attiny-cache.lib
blob: 51dd5d899fe34921801a211a7a858c97116e2ffb (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_AVR-ISP-6
#
DEF Connector_AVR-ISP-6 J 0 40 Y Y 1 F N
F0 "J" -250 450 50 H V L CNN
F1 "Connector_AVR-ISP-6" 0 450 50 H V L CNN
F2 "" -250 50 50 V I C CNN
F3 "" -1275 -550 50 H I C CNN
$FPLIST
 IDC?Header*2x03*
 Pin?Header*2x03*
$ENDFPLIST
DRAW
S -105 -270 -95 -300 0 1 0 N
S -105 400 -95 370 0 1 0 N
S 300 -95 270 -105 0 1 0 N
S 300 5 270 -5 0 1 0 N
S 300 105 270 95 0 1 0 N
S 300 205 270 195 0 1 0 N
S 300 400 -300 -300 0 1 10 f
X MISO 1 400 200 100 L 50 50 1 1 P
X VCC 2 -100 500 100 D 50 50 1 1 P
X SCK 3 400 0 100 L 50 50 1 1 P
X MOSI 4 400 100 100 L 50 50 1 1 P
X ~RST 5 400 -100 100 L 50 50 1 1 P
X GND 6 -100 -400 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Conn_01x01_Female
#
DEF Connector_Conn_01x01_Female J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Conn_01x01_Female" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Connector*:*
$ENDFPLIST
DRAW
A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
P 2 1 1 6 -50 0 -20 0 N
X Pin_1 1 -200 0 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Conn_01x01_Male
#
DEF Connector_Conn_01x01_Male J 0 40 Y N 1 F N
F0 "J" 0 100 50 H V C CNN
F1 "Connector_Conn_01x01_Male" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Connector*:*
$ENDFPLIST
DRAW
S 34 5 0 -5 1 1 6 F
P 2 1 1 6 50 0 34 0 N
X Pin_1 1 200 0 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 LED*
 LED_SMD:*
 LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Q_NMOS_DGS
#
DEF Device_Q_NMOS_DGS Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Device_Q_NMOS_DGS" 200 -50 50 H V L CNN
F2 "" 200 100 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 65 0 110 0 1 10 N
C 100 -70 10 0 1 0 F
C 100 70 10 0 1 0 F
P 2 0 1 0 10 0 -100 0 N
P 2 0 1 10 10 75 10 -75 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 0 100 -100 100 0 30 0 N
P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
P 4 0 1 0 110 20 115 15 145 15 150 10 N
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
X D 1 100 200 100 D 50 50 1 1 P
X G 2 -200 0 100 R 50 50 1 1 I
X S 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_POT
#
DEF Device_R_POT RV 0 40 Y N 1 F N
F0 "RV" -175 0 50 V V C CNN
F1 "Device_R_POT" -100 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
 Potentiometer*
$ENDFPLIST
DRAW
S 40 100 -40 -100 0 1 10 N
P 2 0 1 0 100 0 60 0 N
P 4 0 1 0 45 0 90 20 90 -20 45 0 F
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
X 3 3 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MCU_Microchip_ATtiny_ATtiny85-20PU
#
DEF MCU_Microchip_ATtiny_ATtiny85-20PU U 0 20 Y Y 1 F N
F0 "U" -500 550 50 H V L BNN
F1 "MCU_Microchip_ATtiny_ATtiny85-20PU" 100 -550 50 H V L TNN
F2 "Package_DIP:DIP-8_W7.62mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS ATtiny25-20PU ATtiny45V-10PU ATtiny45-20PU ATtiny85V-10PU ATtiny85-20PU
$FPLIST
 DIP*W7.62mm*
$ENDFPLIST
DRAW
S -500 -500 500 500 0 1 10 f
X ~RESET~/PB5 1 600 -200 100 L 50 50 1 1 B
X XTAL1/PB3 2 600 0 100 L 50 50 1 1 B
X XTAL2/PB4 3 600 -100 100 L 50 50 1 1 B
X GND 4 0 -600 100 U 50 50 1 1 W
X AREF/PB0 5 600 300 100 L 50 50 1 1 B
X PB1 6 600 200 100 L 50 50 1 1 B
X PB2 7 600 100 100 L 50 50 1 1 B
X VCC 8 0 600 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_VCC
#
DEF power_VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_Vdrive
#
DEF power_Vdrive #PWR 0 0 Y Y 1 F P
F0 "#PWR" -200 -150 50 H I C CNN
F1 "power_Vdrive" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X Vdrive 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library
bues.ch cgit interface