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crcgen.git
flexiblesizes
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vhdl
Generator for CRC HDL code (VHDL, Verilog, MyHDL)
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Author
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flexiblesizes
generator test: Add support for data sizes != 8
Michael Buesch
3 years
master
Bump version
Michael Buesch
7 months
vhdl
generator: Add VHDL support
Michael Buesch
3 years
Tag
Download
Author
Age
crcgen-2.6
crcgen-2.6.tar.xz
crcgen-2.6.zip
Michael Buesch
7 months
crcgen-2.5
crcgen-2.5.tar.xz
crcgen-2.5.zip
Michael Buesch
13 months
crcgen-2.4
crcgen-2.4.tar.xz
crcgen-2.4.zip
Michael Buesch
17 months
crcgen-2.3
crcgen-2.3.tar.xz
crcgen-2.3.zip
Michael Buesch
18 months
crcgen-2.2
crcgen-2.2.tar.xz
crcgen-2.2.zip
Michael Buesch
2 years
crcgen-2.1
crcgen-2.1.tar.xz
crcgen-2.1.zip
Michael Buesch
3 years
crcgen-2.0
crcgen-2.0.tar.xz
crcgen-2.0.zip
Michael Buesch
3 years
crcgen-1.1
crcgen-1.1.tar.xz
crcgen-1.1.zip
Michael Buesch
4 years
crcgen-1.0
crcgen-1.0.tar.xz
crcgen-1.0.zip
Michael Buesch
5 years
Age
Commit message
Author
Files
Lines
2021-07-17
Bump version
crcgen-2.1
Michael Buesch
1
-1
/
+1
2021-07-17
Add examples to Readme
Michael Buesch
2
-2
/
+34
2021-07-17
Fix release script
Michael Buesch
1
-1
/
+1
2021-07-17
setup: Update keywords
Michael Buesch
1
-1
/
+2
2021-07-17
Rename main module to libcrcgen
Michael Buesch
12
-17
/
+17
2021-07-16
Fix VHDL bits
Michael Buesch
1
-3
/
+3
2021-07-16
Print language in header
Michael Buesch
1
-8
/
+8
2021-07-16
Reorder options
Michael Buesch
1
-2
/
+2
2021-07-16
Simplify generated Python code
Michael Buesch
1
-10
/
+7
2021-07-16
generator: Add VHDL support
vhdl
Michael Buesch
2
-7
/
+55
[...]
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